Inverse-graded Ge Buffer Layer for Strained Transistor Channels

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Solution Overview

Problem

Current techniques for forming transistor channel materials in integrated circuits face challenges in increasing charge carrier mobility, particularly in non-planar configurations and scaled-down transistors, due to poor mechanical coupling between channel and source/drain regions, and the limitations of using a Si substrate which restricts strain imposition and material diversity.

Innovation Solution

A thin, inverse-graded germanium (Ge)-based layer is used as a template to grow compressively strained PMOS and tensile strained NMOS channel materials, effectively trapping defects near the substrate interface and maintaining strain throughout the channel regions, thereby enhancing hole and electron mobility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a Si substrate is used to form transistor channel materials, then manufacturing simplicity is maintained, but charge carrier mobility and strain imposition are restricted

Engineering Contradiction:
Improvecharge carrier mobilityVSAvoidmaterial diversity and strain imposition
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

A Ge-based buffer layer is introduced as an intermediary between the Si substrate and the channel material. This buffer layer enables strain imposition on the channel material while maintaining compatibility with the Si substrate, thereby improving charge carrier mobility without sacrificing manufacturing simplicity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The lattice parameter of the substrate interface is changed by using a Ge-based buffer layer instead of direct Si substrate. This parameter change enables strain imposition on the channel material, allowing for improved charge carrier mobility and enhanced transistor performance

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If channel materials are grown directly on Si substrate, then process simplicity is maintained, but mechanical coupling between channel and source/drain regions deteriorates in scaled-down transistors

Engineering Contradiction:
Improveprocess simplicityVSAvoidmechanical coupling
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The Ge-based buffer layer serves as a mediator that improves mechanical coupling between the channel material and source/drain regions in scaled-down transistors, while maintaining process simplicity through a straightforward layering approach

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If defects are present at substrate interface, then manufacturing tolerance is relaxed, but channel material quality and mobility deteriorate

Engineering Contradiction:
Improvemanufacturing toleranceVSAvoidchannel material quality
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The Ge-based buffer layer converts the potential harm of defects at the substrate interface into a benefit by trapping these defects within the buffer layer itself. This prevents defects from propagating into the channel material, maintaining high channel material quality and mobility while allowing for relaxed manufacturing tolerances at the substrate interface

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the formation of high-quality channel materials with improved mobility and reduced wafer bowing, enabling co-integration of high-performance PMOS and NMOS devices in CMOS circuits with lower leakage and higher drive currents.

Implementation Method 1

effectively trapping defects near the substrate interface

Methodology Applied
Scientific EffectDefect trapping: Gettering

Implementation Method 2

maintaining strain throughout the channel regions, thereby enhancing hole and electron mobility

Methodology Applied
Scientific EffectStrain: Deformation

Data Source

PatentUS11404575B2Diverse transistor channel materials enabled by thin, inverse-graded, germanium-based layer
Publication Date: 2022.08.02 INTEL CORP
  • US11404575B2 patent drawing
  • US11404575B2 patent drawing
  • US11404575B2 patent drawing

AI summary

Techniques are disclosed for forming diverse transistor channel materials enabled by a thin, inverse-graded, germanium (Ge)-based layer. The thin, inverse-graded, Ge-based layer (e.g., having a thickness of at most 500 nm) can then serve as a template for the growth of compressively strained PMOS channel material and tensile strained NMOS channel material to achieve gains in hole and electron mobility, respectively, in the channel regions of the devices. Such a relatively thin Ge-based layer can be formed with suitable surface quality/relaxation levels due to the inverse grading of the Ge concentration in the layer, where the Ge concentration is relatively greatest near the substrate and relatively lowest near the overlying channel material layer. In addition to the inverse-graded Ge concentration, the Ge-based layer may be characterized by the nucleation, and predominant containment, of defects at/near the interface between the substrate and the Ge-based layer.