Inverse Interleaving Bit Positioning for Bufferless Rate Matching
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Solution Overview
Problem
Existing channel coding techniques require the entire data stream sub-block to be loaded into a middle buffer for interleaving, leading to undesirable latency and the necessity of using a middle buffer, which hinders efficient rate matching and increases power consumption and memory requirements.
Innovation Solution
An integrated circuit with an inverse interleaving module that determines the position of data bits within an interleaved data stream, allowing for on-the-fly rate matching independent of other data bits, thereby eliminating the need for a middle buffer and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the entire data stream sub-block is loaded into a middle buffer for interleaving, then the interleaving operation can be completed, but the latency increases and power consumption increases
Solution Approach 1:
The patent divides the data stream into individual data bits that can be processed independently. The inverse interleaving module calculates the position of each data bit within the interleaved data stream separately, allowing parallel processing without requiring a middle buffer to hold the entire sub-block. This segmentation enables on-the-fly processing of each bit as it becomes available from the turbo encoder.
Solution Approach 2:
The patent pre-calculates and stores the interleaving pattern mapping relationships before processing the actual data. The inverse interleaving module uses these pre-established mappings to directly determine the position of each incoming data bit in the interleaved stream, eliminating the need to wait for complete sub-block assembly and enabling immediate rate matching operations.
2Quantity of substance
If a middle buffer is used to store the entire data stream sub-block, then interleaving can be performed, but memory requirements increase and power consumption increases
Solution Approach 1:
The patent extracts only the necessary information (position of individual data bits) from the interleaving operation rather than processing the entire data sub-block at once. The inverse interleaving module calculates positions of data bits independently as they arrive from the turbo encoder, eliminating the need to store and process the complete sub-block in a middle buffer, thereby reducing memory usage and associated power consumption.
Solution Approach 2:
The system processes data bits as they become available from the turbo encoder without requiring external buffering infrastructure. Each data bit is independently positioned using the inverse interleaving calculation, enabling the system to serve itself with minimal memory resources and reduced power consumption compared to traditional middle buffer architectures.
3Productivity
If rate matching waits for complete turbo encoding and interleaving, then accurate bit selection can be performed, but the processing speed decreases
Solution Approach 1:
The patent enables continuous processing by allowing rate matching operations to begin as soon as individual data bits are available from the turbo encoder, rather than waiting for complete sub-block processing. The inverse interleaving module continuously calculates positions of incoming data bits, enabling the rate matching module to continuously select and place bits in the output buffer without idle waiting periods, thereby maintaining high processing throughput.
Solution Approach 2:
The system performs preliminary setup of the inverse interleaving position calculations before data processing begins. This pre-computation of position mappings allows the rate matching operation to proceed immediately with incoming data bits without requiring waiting time for interleaving completion, significantly improving processing speed while maintaining accurate bit selection.
Data Source
AI summary
An encoding module comprises an inverse interleaving module arranged to: determine an initial location index within an interleaving matrix for a data bit; and perform bit reverse ordering (BRO) on a column index value for the initial location index for the data bit to obtain a BRO column index value for the data bit. The inverse interleaving module is further arranged to calculate a number of valid interleaving matrix addresses preceding a location index for the data bit following bit reverse ordering; and determine a position of the data bit within the interleaved data stream based on the calculated number of valid addresses.