Inverse Optical Lithography Pattern Correction
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Solution Overview
Problem
The complexity of designing and manufacturing photo-masks for integrated circuits increases due to decreasing minimum dimensions, leading to computational challenges and distortions in photolithography processes, where existing techniques like OPC and RET struggle to produce lithographically optimal target patterns.
Innovation Solution
A computer system determines a modified target pattern by calculating polygon parameters and mask patterns using inverse optical calculations, evaluating a cost function to optimize polygon geometry and reduce defects in the photolithographic process, thereby improving yield and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing OPC and RET techniques are used to pre-distort mask patterns, then wafer pattern accuracy is improved, but computational complexity and processing requirements increase significantly
Solution Approach 1:
The patent inverts the traditional OPC approach by using inverse optical calculations to determine mask patterns that will produce the desired target pattern, rather than iteratively adjusting patterns to account for optical distortions. This inversion reduces computational complexity while maintaining manufacturing precision.
Solution Approach 2:
The patent changes the parameter representation from traditional polygon-based mask patterns to level set functions, enabling more efficient computational processing and reducing the complexity of optical proximity correction calculations.
2Productivity
If feature dimensions are decreased to increase circuit density, then circuit integration is improved, but photolithography distortions and artifacts increase
Solution Approach 1:
The patent applies preliminary action by using inverse optical calculations to pre-determine the exact mask pattern needed to compensate for expected photolithography distortions, ensuring accurate pattern transfer even at reduced feature dimensions.
3Ease of manufacture
If traditional polygon-based target patterns are used, then design simplicity is maintained, but lithographic optimality and process window are reduced
Solution Approach 1:
The patent transforms the parameter representation from simple polygons to level set functions, which provide continuous boundary representation and enable better lithographic optimization while maintaining computational tractability through efficient mathematical operations.
Data Source
AI summary
During a calculation technique, at least a portion of a target pattern associated with an integrated-circuit design is modified so that polygons in the target pattern, which represent features in the design, result in acceptable accuracy during a photolithographic process that fabricates the target pattern on a semiconductor die. In particular, a set of polygon parameters associated with the polygons are modified, as needed, so that a cost function that corresponds to a difference between a modified target pattern and an estimated target pattern produced during the photolithographic process meets a termination criterion. A mask pattern that can fabricate the modified target pattern on the semiconductor die is calculated using an inverse optical calculation in which the modified target pattern is at an image plane of an optical path associated with the photolithographic process and the mask pattern is at an object plane of the optical path.