Inverse-Redundant Logic Cells for Soft-Error Filtering
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Solution Overview
Problem
Current radhard-by-design technologies for single event errors in ultra-deep submicron technologies face challenges in efficiently reducing soft errors, particularly in logic circuits, due to increased sensitivity to radiation and high feature integration, leading to undesirable power and area overheads, and inability to handle multiple bit upsets or single-event multiple upsets effectively.
Innovation Solution
The development of inverse-redundant (IR) and combined-dual-inverse-redundant (CDIR) logic cells and circuits, which utilize both the original and inverse data signals to create a novel layout arrangement that filters out errors by ensuring no single error generates errors on both outputs, thereby reducing soft-error rates without additional power or area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triplication (TMR) or duplication (BiSER) techniques are used to protect against single event errors, then reliability is improved, but power and area overhead increase
Solution Approach 1:
The patent combines the original logic circuit with its inverse circuit into a unified structure where both circuits share common resources and layout space. The inverse circuit is constructed using complementary transistors that can be integrated with the original circuit's transistors, merging functionality while reducing overall area overhead compared to separate duplication approaches.
Solution Approach 2:
The patent utilizes the inverse logic circuit (complement of original logic) to create a self-correcting system. By constructing the inverse circuit using complementary transistors and combining it with the original circuit, the system leverages the inverse relationship to filter errors - when a single event upset occurs in one circuit, the other circuit produces the opposite erroneous output, allowing error detection and correction through comparison.
2Productivity
If feature integration and frequency are increased, then productivity is improved, but soft-error rates increase due to larger spatial distribution and pulse length of SET
Solution Approach 1:
The patent performs preliminary error filtering by combining the original and inverse circuits in a layout arrangement that prevents single event transients from propagating as errors. The complementary transistor configuration and interlocked layout are designed in advance to cancel out SET effects before they can latch into storage elements or propagate through the circuit.
Solution Approach 2:
The patent creates a composite circuit structure combining original and inverse logic circuits with complementary transistor configurations. This composite structure leverages the opposing characteristics of the two circuits to cancel out the effects of single event transients, similar to how composite materials combine different properties to achieve superior performance.
3Ease of manufacture
If standard commercial semiconductor manufacturing is used, then ease of manufacture is improved, but ability to handle MBUs or SEMUs is limited
Solution Approach 1:
The patent segments the logic circuit into original and inverse portions that can be independently designed and manufactured using standard processes. The layout arrangement separates critical nodes and transistors in a way that limits the propagation of multiple bit upsets, allowing standard commercial manufacturing to be used while still providing protection against MBUs and SEMUs.
Data Source
AI summary
A method is disclosed for creating a logic integrated circuit cell from an original logic integrated circuit gate. The method includes combining the original logic integrated circuit cell with a second circuit which takes as input a complement of inputs of the original logic integrated circuit cell and provides as output complements of the output of the original logic integrated circuit cell. The method further includes connecting the combined logic integrated circuit cells, where the outputs of the combined integrated circuit cells provide the inputs for other combined circuit cells such that, when the output of the original logic integrated circuit from a first combined logic integrated circuit cell is connected as input to a second combined logic integrated circuit cell, then the output of the second circuit in the first combined logic integrated circuit cell is always also connected to the second combined logic integrated circuit cell serving as the inverse of the input signals that come from the original logic integrated circuit cell.