Inverse-Sinc DAC Compensation Using Low-Rate Interleaved Filtering
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Solution Overview
Problem
High-speed digital systems face inefficiencies when implementing inverse-sinc filters due to the need for high-speed pipelining hardware, which increases power dissipation, integrated-circuit area, and complexity, making it costly to process signals from interleaved sub-systems.
Innovation Solution
A four-input, four-output integrated inverse-sinc module operates at a lower data rate, processing discrete-time input signals to generate equivalent interleaved sequences, reducing hardware demands and costs by sharing delay elements and using sub-expression sharing techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed pipelining hardware is used to implement inverse-sinc filters at high data rates, then processing speed is improved, but power dissipation increases
Solution Approach 1:
The patent divides the high-speed filtering task into multiple parallel low-speed subsystems, each processing a subset of data at lower data rates. The outputs are then interleaved to reconstruct the high-speed signal. This segmentation allows inverse-sinc filtering to be performed at lower data rates in each subsystem, reducing power dissipation while maintaining overall high-speed performance.
2Speed
If high-speed pipelining hardware is used to implement inverse-sinc filters, then processing speed is improved, but integrated-circuit area increases
Solution Approach 1:
The patent segments the filtering function across multiple parallel subsystems operating at lower speeds. Each subsystem requires less hardware resources than a single high-speed system, reducing the total integrated-circuit area. The parallel architecture with interleaved outputs achieves high-speed performance without requiring large-area high-speed pipelining hardware in each processing path.
3Speed
If high-speed pipelining hardware is used to implement inverse-sinc filters, then processing speed is improved, but device complexity increases
Solution Approach 1:
The patent divides the complex high-speed filtering task into simpler parallel subsystems operating at lower speeds. Each subsystem implements inverse-sinc filtering with reduced complexity requirements. The overall system complexity is managed through the parallel architecture and interleaving mechanism, which is simpler than implementing full high-speed pipelining in a single processing path.
4Productivity
If multiple parallel subsystems are used to achieve high-speed operation through interleaving, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple parallel subsystems' outputs through an interleaving mechanism to produce a high-speed output stream. This combining approach achieves high productivity by aggregating the output rates of multiple lower-speed subsystems, while the interleaving structure provides a systematic method to manage the complexity of coordinating multiple parallel processing paths.
Data Source
AI summary
A method and system for the design and implementation of an inverse-sinc function that can efficiently process signals produced by high-speed systems is presented. An integrated inverse-sinc module accepts multiple data streams that may result from parallel sub-systems and creates multiple outputs that can be interleaved to produce a sequence that has been filtered by an inverse-sinc function. The multiple-input, multiple-output system may be beneficially operated at a low data rate, such as the data rate used by each of the sub-systems.