Inverse Sparse FFT Permutation Filtering for GPS L5 Acquisition
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Solution Overview
Problem
Existing GPS receivers face challenges in efficiently performing permutation and filtering steps in inverse sparse fast Fourier transforms, particularly for L5 frequency signals, which require higher sampling rates and longer FFT lengths, leading to increased memory usage and processing time.
Innovation Solution
A signal processing device and method that utilizes an input counter, address ROM, comparator, address counter, window memory, and multipliers with minimal signed digit representation to optimize permutation and filtering, reducing the number of multipliers and redesigning the filter to include only barrel shifters and adders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional permutation and filtering methods are used in inverse sparse fast Fourier transform, then processing accuracy is maintained, but memory usage increases and processing speed decreases
Solution Approach 1:
The permutation operation is divided into multiple stages with different permutation parameters (first permutation parameter and second permutation parameter). The filtering operation is segmented into parallel processing paths. This segmentation allows the system to process data in smaller chunks, reducing peak memory requirements while maintaining processing throughput.
Solution Approach 2:
The patent transforms the traditional time-domain filtering approach into a frequency-domain operation using the sparse FFT structure. By operating in the frequency domain and utilizing the sparsity property, the system reduces computational complexity and memory access requirements compared to conventional time-domain filtering methods.
2Reliability
If conventional permutation and filtering methods are used in inverse sparse fast Fourier transform, then processing accuracy is maintained, but hardware complexity increases
Solution Approach 1:
Permutation parameters are predetermined and pre-configured in the system. The first permutation parameter and second permutation parameter are established before signal processing begins, allowing the hardware to operate with fixed, optimized configurations rather than dynamic reconfiguration, thereby reducing hardware complexity while maintaining processing accuracy.
Solution Approach 2:
The patent utilizes changes in permutation parameters across different processing stages to achieve the desired signal transformation. By varying these parameters systematically, the system maintains high processing quality while using simpler hardware structures compared to conventional approaches that require complex adaptive filtering elements.
3Measurement precision
If longer FFT length is used for L5 signals, then signal acquisition accuracy improves, but processing time increases
Solution Approach 1:
The patent extracts and processes only the significant frequency components corresponding to the sparse signal structure. By identifying and focusing computational resources on the relevant frequency bins rather than processing the entire FFT spectrum, the system achieves accurate L5 signal acquisition with reduced processing time despite using longer FFT lengths.
Solution Approach 2:
The system performs partial processing by utilizing the sparsity property to process only the necessary portions of the signal. The inverse sparse FFT computes only the significant time-domain samples needed for GPS signal acquisition rather than computing the complete transform, thereby reducing processing time while maintaining measurement precision for L5 signals.
Data Source
AI summary
A signal processing device for an inverse sparse fast Fourier transform performing permutation and filtering is disclosed. The signal processing device acquires a signal and converts the acquired signal into a time domain. The signal processing device comprises an input counter configured to give an index to the acquired signal; an address ROM configured to store signal information based on a predetermined first permutation parameter and a predetermined second permutation parameter used for a data order change; a comparator configured to check whether the index given to the acquired signal matches the signal information stored in the address ROM; an address counter configured to transmit an output signal to the address ROM when the comparator acquires a matching signal, and count a number of transmissions; a window memory configured to acquire different signals from the address ROM and output different window coefficients replaced in a minimal signed digit (MSD) representation representing a number in limited nonzero digits; and two multipliers configured to multiply the acquired signals by the window coefficients and output the signals.