Inverse Tapered Source Electrode for Vertical Transistors
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Solution Overview
Problem
In vertical transistors with trench gate structures, reducing the pitch of gate trenches to increase integration leads to reduced overlap between source regions and electrodes, resulting in increased contact resistance and on-resistance.
Innovation Solution
The contact region of the source electrode is designed with an inverse tapered shape, increasing the contact area between the source electrode and source region, and the manufacturing method involves forming inverse tapered openings and sidewalls to ensure proper alignment and reduce on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch of gate trenches is reduced to increase integration, then the degree of integration is improved, but the overlap area between source region and source electrode is reduced
Solution Approach 1:
The source electrode is designed with an inverse tapered shape where the width at the lower end (contacting source region) is greater than the width at the upper end. This dimensional change in the vertical direction allows the electrode to maintain sufficient contact area with the source region even when the horizontal pitch between gate trenches is reduced, thus resolving the contradiction between integration density and contact area.
Solution Approach 2:
The shape parameter of the source electrode is changed from a conventional rectangular or tapered shape to an inverse tapered shape. This parameter change ensures that the electrode width varies along the vertical axis, with the broader lower portion providing adequate overlap with the source region while the narrower upper portion accommodates reduced pitch requirements, thereby maintaining both high integration and sufficient contact area.
2Productivity
If the pitch of gate trenches is reduced to increase integration, then the degree of integration is improved, but the contact resistance increases
Solution Approach 1:
By changing the vertical dimensioning of the source electrode through inverse tapering, the contact area with the source region is maintained at adequate levels even when horizontal spacing is reduced. This ensures sufficient charge carrier transport pathways, preventing contact resistance from increasing despite higher integration density.
Solution Approach 2:
The geometric parameters of the source electrode are optimized by implementing an inverse tapered profile, where the width ratio between lower and upper ends is controlled to ensure minimum contact area requirements are met. This parameter optimization maintains low contact resistance while enabling reduced gate trench pitch for higher integration.
3Productivity
If the pitch of gate trenches is reduced to increase integration, then the degree of integration is improved, but the on-resistance increases
Solution Approach 1:
The inverse tapered shape of the source electrode modifies the vertical distribution of current flow by providing a broader contact area at the lower end. This dimensional adjustment ensures adequate current carrying capacity and reduces on-resistance even when the device is scaled to achieve higher integration density through reduced gate trench pitch.
Solution Approach 2:
By optimizing the width ratio parameter of the inverse tapered source electrode, the current distribution and resistance characteristics are improved. The parameter control ensures that sufficient conductive pathways are maintained, preventing on-resistance increase while achieving the desired integration density through pitch reduction.
Data Source
AI summary
A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane; a first and a second electrode; first, second, and third semiconductor regions; first and second gate electrodes in the semiconductor layer; first and second gate insulating films; and an insulating layer provided between the first and second gate electrodes and the first electrode. The first electrode has a first region and a second region. The first region contacts the semiconductor layer. The first region is located between the second region and the first semiconductor region. A first part of the first region is located between the first gate electrode and the second gate electrode. A second part of the first region is interposed between a first portion and a second portion of the insulating layer. The second part of the first region has an inverse tapered shape.