Inversion-Based ECC Scheme for MRAM Partial-Short Defects
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Solution Overview
Problem
Existing error correction techniques for memory devices, such as MRAM, are inadequate in addressing biased manufacturing defects that cause partial shorts, limiting their effectiveness in correcting errors.
Innovation Solution
Implementing an error correction code scheme that includes a Bose-Chaudhuri-Hocquenghem (BCH) algorithm and hardware construction to produce invertible ECC codewords, which allows for the detection and correction of partial shorts by inverting data when necessary, thereby enhancing error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction techniques are used, then basic error correction is provided, but biased manufacturing defects causing partial shorts cannot be effectively corrected
Solution Approach 1:
The patent applies inversion by detecting biased manufacturing defects and inverting the data bits that are affected by partial shorts. When a defect is detected in a specific bit position, the system inverts all data bits to correct the erroneous readings caused by the partial short, effectively using the opposite operation to counteract the manufacturing defect.
Solution Approach 2:
The patent performs preliminary detection of biased manufacturing defects during the write operation before the data is fully stored. By detecting defects in advance and preparing inversion operations beforehand, the system can correct errors proactively rather than reactively, improving overall error correction effectiveness.
2Reliability
If two-layer ECC without inversion is used, then two corrections and one detection are guaranteed in first layer and one correction in second layer, but biased manufacturing defects are not adequately addressed
Solution Approach 1:
The patent enhances the two-layer ECC approach by incorporating data inversion operations. When partial shorts are detected in either ECC layer, the system inverts the affected data bits to correct the errors, going beyond the standard correction capabilities of conventional two-layer ECC schemes.
Solution Approach 2:
The patent changes the operational parameters of the ECC system by dynamically selecting between standard correction modes and inversion modes based on the detected error patterns. This allows the system to adapt its correction strategy to match the specific characteristics of manufacturing defects, improving overall reliability.
3Reliability
If advanced error correction schemes are implemented, then more errors can be corrected, but device complexity and area increase
Solution Approach 1:
The patent extracts and addresses only the specific problem of biased manufacturing defects caused by partial shorts, rather than implementing a full-blown advanced error correction scheme. By focusing on detecting and correcting this particular defect type through targeted inversion operations, the system achieves improved reliability without the full complexity of comprehensive advanced ECC schemes.
Solution Approach 2:
The patent segments the error correction process into distinct stages: defect detection, inversion decision-making, and selective inversion execution. This segmentation allows the system to implement complex error correction functionality in a modular, manageable way that doesn't excessively increase overall device complexity.
4Reliability
If comprehensive error correction is implemented, then more errors are corrected, but power consumption and area increase
Solution Approach 1:
The patent applies partial action by implementing inversion operations only when and where needed - specifically when biased manufacturing defects are detected in certain bit positions. Rather than continuously inverting all data or implementing power-intensive comprehensive error correction, the system selectively applies inversion only to affected portions, reducing overall power consumption while maintaining effective error correction.
Data Source
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AI summary
A method of correcting one or more errors in a memory device, the method performed by one or more controllers. The method may receive data. The method may further write bits at a memory location to a first state. The method may further read respective values of the bits at the memory location. The method may further determine an error correction based on the respective values. The method may further write the received data to the memory location as received data or inverted data, based on the error correction.