Inversion Signal Circuit for Low-Transition High-Speed Data Buses

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Solution Overview

Problem

Existing semiconductor design technologies face challenges in efficiently generating inversion signals during high-speed data transmission, leading to increased current consumption and noise due to frequent data transitions, which the DBI technology partially addresses but not comprehensively.

Innovation Solution

A circuit design incorporating transition detection signal generation circuits and XOR gates to generate pre-inversion signals, followed by alignment circuits to produce inversion signals, optimizing the number of transitions and reducing delays in signal generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is transmitted at high speed through the channel, then transmission efficiency is improved, but current consumption increases and noise is generated due to frequent data transitions

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidcurrent consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies DBI technology by inverting the data signal when the number of transitions exceeds a threshold. The inversion signal generation circuit monitors transition counts and inverts the data bus signals accordingly, transforming the problem of excessive transitions into a controlled inversion operation that reduces overall transitions and associated current consumption

Inventive Principle:
Principle #13The other way round (Inversion)

2Loss of energy

If the number of data transitions is reduced using DBI technology, then current consumption and noise are reduced, but device complexity increases due to additional inversion signal generation circuits

Engineering Contradiction:
Improvecurrent consumptionVSAvoidcircuit complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The inversion signal generation circuit is segmented into modular components: transition detection units that count transitions, comparison logic that evaluates against thresholds, and inversion control units that generate control signals. This segmentation allows the complex function to be distributed across manageable modules, reducing overall circuit complexity while maintaining effectiveness

Inventive Principle:
Principle #1Segmentation

3Productivity

If transition detection and inversion operations are performed comprehensively, then data transmission efficiency is improved, but signal generation delay increases

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidsignal generation delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The circuit performs preliminary transition counting and evaluation during the data transmission setup phase, before the actual data transfer begins. By pre-determining whether inversion is needed and generating the inversion control signal in advance, the circuit avoids delays during critical data transmission windows, thus reducing signal generation delay while maintaining transmission efficiency

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11152042B2Inversion signal generation circuit
Publication Date: 2021.10.19 SK HYNIX INC
  • US11152042B2 patent drawing
  • US11152042B2 patent drawing
  • US11152042B2 patent drawing

AI summary

An inversion signal generation circuit may include a transition detection signal generation circuit suitable for generating first to fourth transition detection signals, a first XOR gate suitable for receiving a fourth inversion signal and the first transition detection signal, and generating a first pre-inversion signal, a second XOR gate suitable for receiving the first pre-inversion signal and the second transition detection signal, and generating a second pre-inversion signal, a third XOR gate suitable for receiving the second transition detection signal and the third transition detection signal, a fourth XOR gate suitable for receiving the first pre-inversion signal and an output signal of the third XOR gate, and generating a third pre-inversion signal, a fifth XOR gate suitable for receiving the third pre-inversion signal and the fourth transition detection signal, and generating a fourth pre-inversion signal, and a first alignment circuit suitable for generating first to fourth inversion signals.