Inversion Mode Varactor Backgate Bias for Low Series Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Inversion mode varactors in fully-depleted silicon-on-insulator (FDSOI) structures face challenges in achieving high quality factor due to high series resistance in the transition regime from depletion to inversion, limiting their performance in analog applications.
Innovation Solution
The introduction of a backgate layer close to the buried oxide interface in the FDSOI inversion mode varactor, with a selectively controlled bias voltage, forms an inversion region that maintains low series resistance and enhances the quality factor by shifting the charge centroid from the back interface to the front interface as the gate voltage increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional FDSOI inversion mode varactor is used, then the device structure is simple, but the series resistance is high in the transition regime from depletion to inversion, resulting in low quality factor
Solution Approach 1:
The patent segments the gate control into two independent parts: a front gate and a backgate. This segmentation allows independent control of the inversion region formation, enabling the channel to be pinned in strong inversion at the back interface while maintaining capacitance modulation through front gate voltage, thereby achieving low series resistance and high quality factor throughout the capacitance range
Solution Approach 2:
The backgate acts as an intermediary element that mediates the control of inversion charge at the back interface. By applying a fixed bias to the backgate, it creates and maintains the inversion region that serves as an intermediate conductive path, reducing series resistance without requiring complex additional structures
2Reliability
If the gate voltage is increased to move the charge centroid from the back interface to the front interface, then the capacitance increases, but the series resistance increases in the transition regime, reducing the quality factor
Solution Approach 1:
The backgate bias is applied in advance to pre-form the inversion region at the back interface before capacitance modulation begins. This preliminary action ensures that a conductive path exists throughout the capacitance modulation range, preventing series resistance from increasing during the transition from depletion to inversion
Solution Approach 2:
The patent changes the control parameter from single-gate voltage to dual-gate voltages (front gate and backgate). By independently controlling both gates, the system can maintain the channel in a pinned inversion state at the back interface while still achieving capacitance modulation through front gate voltage changes, keeping series resistance low across the entire capacitance range
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves the quality factor of the varactor by maintaining low series resistance across the capacitance range, particularly in the weak inversion region, thereby enhancing its performance in analog applications.
Implementation Method 1
applying a bias voltage to the backgate layer to form an inversion region in the semiconductor layer at an interface between the semiconductor layer and the insulating layer
Implementation Method 2
a gate stack defining a channel between the source region and the drain region
Implementation Method 3
This results in the formation of a depletion region between the anode and cathode that behaves as the dielectric of the device
Implementation Method 4
capacitance is inversely proportional to dielectric thickness
Data Source
AI summary
In one exemplary embodiment of the invention, a method includes: providing an inversion mode varactor having a substrate, a backgate layer overlying the substrate, an insulating layer overlying the backgate layer, a semiconductor layer overlying the insulating layer and at least one metal-oxide semiconductor field effect transistor (MOSFET) device disposed upon the semiconductor layer, where the semiconductor layer includes a source region and a drain region, where the at least one MOSFET device includes a gate stack defining a channel between the source region and the drain region, where the gate stack has a gate dielectric layer overlying the semiconductor layer and a conductive layer overlying the gate dielectric layer; and applying a bias voltage to the backgate layer to form an inversion region in the semiconductor layer at an interface between the semiconductor layer and the insulating layer.