Inverted IC Chip Assembly With Edge Conductive Features
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Solution Overview
Problem
Existing integrated circuit chip packaging methods fail to effectively protect the chip mechanically and environmentally while ensuring electrical interconnection, as contacts on the top surface complicate the integration with package elements and spacers, leading to suboptimal cavity formation and conductive feature extension.
Innovation Solution
The method involves positioning a package element below an integrated circuit chip with a spacer element between them, forming a closed cavity, and extending conductive features from the chip's contacts along the top and edge surfaces to connect with the package element, allowing for efficient electrical interconnection and enhanced protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contacts are placed on the top surface of the chip, then electrical interconnection is enabled, but the integration with package elements becomes complicated
Solution Approach 1:
The chip is inverted so that contacts exposed at the top surface face away from the package element, allowing conductive features to extend along the edge surfaces rather than requiring complex routing around the chip perimeter, thus simplifying integration while maintaining electrical interconnection
2Reliability
If leads extend from conductive pads around edge and bottom surfaces, then electrical interconnection is achieved, but mechanical protection is suboptimal
Solution Approach 1:
Conductive features are extended along the vertical edge surfaces of the chip rather than only along the horizontal bottom surface, utilizing the vertical dimension to achieve electrical interconnection while allowing the package element to provide superior mechanical and environmental protection from below
3Object-affected harmful factors
If a cavity is formed between package element and chip, then environmental protection is improved, but cavity formation becomes complex with top-surface contacts
Solution Approach 1:
By inverting the chip orientation, the cavity can be formed in a straightforward manner with the package element positioned below the chip, supported by spacers, eliminating the complexity of forming cavities around top-surface contacts while maintaining environmental protection
Data Source
AI summary
The present invention provides an integrated circuit chip assembly and a method of manufacturing the same. The assembly includes a package element having a top surface and an integrated circuit chip having a top surface, a bottom surface, edge surface between the top and bottom surfaces, and contacts exposed at the top surface. The package element is disposed below the chip with the top surface of the package element facing toward the bottom surface of the chip. At least one spacer element resides between the top surface of the package element and the bottom surface of the chip. According to one embodiment, the at least one spacer element may form a substantially closed cavity between the package element and the integrated circuit chip. According to another embodiment, first conductive features may extend from the contacts of the chip along the top surface, and at least some of said first conductive features extend along at least one of the edge surfaces of the chip.