Dynamic Inverted-Output D Flip-Flop With Tri-State Latches
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Solution Overview
Problem
Current D flip-flops used in Bitcoin mining processes are inefficient due to their design, leading to increased chip area, power consumption, and reduced computation speed, making them unsuitable for modern mining requirements.
Innovation Solution
The development of a dynamic D flip-flop with an inverted output, which reduces chip area and power consumption by omitting an input inverter and utilizing a tri-state latch design, thereby improving computation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional D flip-flop design is used, then the output function is correct, but the chip area and power consumption are increased
Solution Approach 1:
The patent extracts and removes the input inverter from the conventional D flip-flop structure. By taking out this redundant component, the chip area is reduced while the core functionality is preserved through the modified latch structure that directly processes the D input without requiring separate inversion logic.
Solution Approach 2:
The patent merges the inversion function into the latch structure itself. Instead of having a separate inverter stage before the latch, the inversion operation is integrated within the latch's internal logic, combining multiple functions into a single unified structure that reduces overall component count.
2Use of energy by stationary object
If a conventional D flip-flop design is used, then the output function is correct, but the power consumption is increased
Solution Approach 1:
The patent extracts and removes the input inverter from the conventional D flip-flop structure. By taking out this redundant component, the chip area is reduced while the core functionality is preserved through the modified latch structure that directly processes the D input without requiring separate inversion logic.
Solution Approach 2:
The patent merges the inversion function into the latch structure itself. Instead of having a separate inverter stage before the latch, the inversion operation is integrated within the latch's internal logic, combining multiple functions into a single unified structure that reduces overall component count.
3Speed
If a conventional D flip-flop design is used, then the structure is complete, but the computation speed is reduced
Solution Approach 1:
The patent extracts and removes the input inverter from the conventional D flip-flop structure. By taking out this redundant component, the chip area is reduced while the core functionality is preserved through the modified latch structure that directly processes the D input without requiring separate inversion logic.
Solution Approach 2:
The patent merges the inversion function into the latch structure itself. Instead of having a separate inverter stage before the latch, the inversion operation is integrated within the latch's internal logic, combining multiple functions into a single unified structure that reduces overall component count.
Data Source
AI summary
A dynamic D flip-flop with an inverted output involves an input end (101) used for receiving input data; an output end (102) used for providing output data to respond to the input data; a clock signal end (103) used for receiving a clock signal; a first latch (104) used for latching the input data from the input end (101) and performing inverting transmission on the input data under the control of the clock signal; a second latch (105) used for latching data from the first latch (104) and performing inverting transmission on the data latched by the first latch (104) under the control of the clock signal; and an inverter (106) used for performing inverting output on the data received from the second latch (105), the first latch (104), the second latch (105), and the inverter (106) being sequentially connected in series between the input end and the output end.