Inverted Data Line Pairs for NAND Flash Capacitive Coupling
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Solution Overview
Problem
In NAND flash memory devices, capacitive coupling between floating gates during programming cycles can lead to unintended changes in the threshold voltage levels of memory cells, affecting data integrity, particularly in multi-level memory cells where small voltage changes can alter data values.
Innovation Solution
The implementation of alternating pairs of inverted and non-inverted data lines in the memory array, where the orientation of bit lines is inverted relative to each other, reduces capacitive coupling by applying different potentials to even and odd bit lines, thereby controlling the programming environment to prevent unwanted shifts in threshold voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional data line configuration is used in NAND flash memory, then the memory array structure is simple, but capacitive coupling between floating gates causes unintended threshold voltage changes during programming
Solution Approach 1:
The data line configuration is segmented into alternating pairs of inverted and non-inverted lines. Each pair is treated as a distinct unit with specific orientation, allowing the memory array to manage capacitive coupling effects locally while maintaining overall structure. This segmentation enables selective application of different potential configurations to adjacent bit lines during programming operations.
Solution Approach 2:
The patent introduces asymmetry by inverting the orientation of alternating data lines in paired configurations. Instead of uniform parallel alignment, adjacent bit lines within pairs have opposite orientations, creating an asymmetric pattern that reduces capacitive coupling between floating gates of adjacent memory cells. This asymmetric arrangement is systematically applied throughout the memory array.
2Manufacturing precision
If inverted data line pairs are implemented, then capacitive coupling is reduced and programming precision is improved, but the data line configuration becomes more complex
Solution Approach 1:
The inverted data line pair configuration applies different orientations to specific local regions (alternating pairs) rather than uniformly across the entire array. This local differentiation allows precise control of capacitive coupling effects in specific areas while maintaining simpler configurations in other regions, optimizing programming precision where needed without unnecessarily complicating the overall structure.
Solution Approach 2:
The patent systematically inverts the orientation of alternating data lines, applying the inversion principle to create pairs where one line has normal orientation and the adjacent line has inverted orientation. This inversion strategy directly addresses capacitive coupling issues by reversing the spatial relationship between adjacent bit lines, thereby reducing unwanted electrical interaction between floating gates.
3Stability of the object's composition
If alternating potentials are applied to even and odd bit lines, then threshold voltage stability is improved, but the control circuit complexity increases
Solution Approach 1:
The patent implements periodic action by applying alternating potentials to even and odd bit lines in a systematic, repeating pattern. During programming operations, adjacent bit lines receive different potentials in an alternating sequence that corresponds to the inverted pair configuration. This periodic potential application stabilizes threshold voltages by preventing cumulative capacitive coupling effects while maintaining a regular, predictable control rhythm.
Solution Approach 2:
The inverted data line pair configuration enables equipotentiality strategies by allowing adjacent bit lines to be maintained at different potentials during programming. By systematically assigning different potential levels to even and odd lines within inverted pairs, the control circuit can create equipotential regions that minimize voltage-induced capacitive coupling, thereby stabilizing threshold voltages across the memory array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes the likelihood of over-programming and ensures more precise control over the programming process, maintaining data integrity by reducing capacitive coupling-induced changes in threshold voltage levels, thus enhancing the reliability of multi-level memory cell programming.
Implementation Method 1
capacitive coupling between floating gates during programming cycles can lead to unintended changes in the threshold voltage levels of memory cells
Data Source
AI summary
At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is coupled to the first column of memory cells.