Inverted Dual-GaN Cascode Package for Stable Fast Switching
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Solution Overview
Problem
Existing semiconductor devices with GaN HEMT technology face challenges in achieving stable performance and reducing package resistance and parasitic inductances, especially in multiple fast switching packaged devices with parallel layouts.
Innovation Solution
A semiconductor device comprising a MOSFET die and two GaN dies arranged in a cascode configuration, where the first GaN die is positioned normally and the second GaN die is inverted, with a clip-bonded design that connects the gates of both GaN dies to the MOSFET source and uses a common drain terminal, enhancing thermal control and reducing package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple GaN HEMT devices are arranged in parallel layout for fast switching applications, then switching speed and power handling capability are improved, but performance stability deteriorates due to difficulty in achieving stable performance
Solution Approach 1:
The patent transitions from a planar parallel layout to a three-dimensional stacked configuration where GaN HEMT devices are vertically arranged on top of a silicon MOSFET device. This vertical stacking in the third dimension allows multiple high-speed GaN devices to operate in parallel while maintaining performance stability through improved thermal management and reduced parasitic effects compared to traditional parallel layouts.
2Ease of manufacture
If traditional through-hole packages are used for GaN HEMT devices, then manufacturing simplicity is maintained, but package resistance and parasitic inductances increase along with device size
Solution Approach 1:
The patent replaces the traditional through-hole mechanical packaging approach with a surface mount configuration using copper clip interconnects. The copper clips provide low-inductance electrical connections that directly bond to the device terminals, eliminating the need for long through-hole traces and significantly reducing package resistance and parasitic inductances while maintaining manufacturing feasibility.
3Device complexity
If GaN HEMT devices are operated in their natural depletion mode, then device simplicity is maintained, but safety and control are compromised due to naturally 'on' state
Solution Approach 1:
The patent merges a silicon MOSFET device with GaN HEMT devices in a stacked configuration where the MOSFET operates as a control element in enhancement mode (naturally off state) and the GaN HEMTs operate as power switching devices. The MOSFET's source is connected to the gates of the GaN HEMTs, allowing the MOSFET to control the GaN devices while providing inherent safety through its naturally off state, thus combining simplicity with improved safety and control.
Data Source
Figure 1a~1b
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AI summary
The present invention relates to a semiconductor device comprising a MOSFET die, a first GaN die and a second GaN die. The first GaN die and the second GaN die are arranged in a cascode arrangement. The second GaN die is positioned in an inverted orientation. The MOSFET die controls the first GaN die and the second GaN die.