Inverted Top-Tier FET Stacking for Dense 3D Inter-Tier Connectivity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing 2D semiconductor fabrication methods face scaling challenges as they approach single digit nanometer nodes, necessitating a transition to three-dimensional (3D) semiconductor circuits where transistors are stacked on top of each other to increase transistor density.
Innovation Solution
A multi-tier semiconductor structure is developed with vertically stacked semiconductor device tiers connected by monolithic inter-tier vias and signal wiring structures, utilizing a silicon-on-insulator layer and dense nano-scale connectivity through diffusion break regions, enabling dense inter-tier connectivity while maintaining device placement density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D scaling efforts are used to increase transistor density, then transistor integration is improved, but manufacturing precision and device performance deteriorate at single digit nanometer nodes
Solution Approach 1:
The patent transitions from two-dimensional planar transistor layouts to three-dimensional vertically stacked transistor structures. Multiple tiers of transistors are stacked above each other along the vertical dimension, enabling continued scaling of transistor density without further reducing lateral feature sizes to the point where manufacturing precision deteriorates. The inter-tier vias connect different vertical levels,实现ing 3D integration while maintaining manufacturable lateral dimensions.
2Adaptability or versatility
If heterogeneous functional circuits are integrated onto the same substrate, then circuit functionality is improved, but area utilization and device placement density worsen
Solution Approach 1:
The patent utilizes vertical stacking to integrate heterogeneous functional circuits (such as logic circuits and memory circuits) in the third dimension rather than spreading them out laterally. Different tiers can contain different functional blocks, allowing high-level circuit integration while maintaining compact lateral footprint. The inter-tier via structure enables efficient interconnection between different functional blocks at different vertical levels.
3Adaptability or versatility
If inter-tier vias are formed to connect signal wiring structures, then connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the interconnection structure into distinct components: signal wiring structures on each tier, inter-tier vias for vertical connections, and insulation layers for electrical isolation. This segmentation allows each component to be optimized and fabricated using specialized processes, making the overall complex 3D structure more manufacturable through modular fabrication approaches.
Solution Approach 2:
The patent introduces intermediate insulation layers between tiers that contain embedded via structures. These intermediary layers serve as mediation between the upper and lower tiers, providing a structured approach to forming inter-tier connections. The via structures within the insulation layers act as intermediaries that simplify the connection process between signal wiring structures on different tiers.
Data Source
AI summary
Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first semiconductor device tier that includes first semiconductor devices. A first signal wiring structure can be formed over and electrically connected to the first semiconductor device tier. An insulator layer can be formed over the first signal wiring structure. A second semiconductor device tier can be formed over the insulator layer, the second semiconductor device tier including second semiconductor devices. A second signal wiring structure can be formed over and electrically connected to the second semiconductor device tier. An inter-tier via can be formed vertically through the insulator layer and electrically connecting the second signal wiring structure to the first signal wiring structure. The first semiconductor device tier, the second semiconductor device tier and the inter-tier via can be formed monolithically.