Stacked Inverted Flip Chip Package Height Minimization

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Solution Overview

Problem

Stacked flip chip packages increase in height due to the mounting of a second die on top of a first die, which is not ideal for reducing footprint.

Innovation Solution

A stacked inverted flip chip package design where a secondary electronic component is placed between the primary electronic component and the substrate, using secondary flip chip bumps to electrically and physically couple the components, minimizing the overall height by utilizing a substrate with a secondary electronic component opening and underfill material to secure the components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If a second die is mounted on top of a first die in a stacked package, then the footprint is reduced, but the overall height of the package increases

Engineering Contradiction:

ImprovefootprintVSAvoidoverall height

Core Design Contradiction:

Area of stationary objectVSLength of stationary object

Solution Approach 1:

The patent inverts the conventional stacking approach by placing the secondary electronic component between the substrate and the primary electronic component, rather than on top of it. This inversion allows the package height to be minimized while maintaining the footprint reduction benefit, as the secondary component utilizes the vertical space within the substrate thickness rather than extending beyond it.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent embeds the secondary electronic component within the substrate structure, nesting it between the substrate and primary component. This nesting approach allows multiple components to occupy overlapping vertical spaces, reducing the overall package height while maintaining electrical connectivity through the substrate.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Length of stationary object

If a secondary electronic component is placed between the primary electronic component and the substrate, then the package height is minimized, but the manufacturing complexity increases

Engineering Contradiction:

Improvepackage heightVSAvoidmanufacturing complexity

Core Design Contradiction:

Length of stationary objectVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by forming openings in the substrate and preparing mounting surfaces before assembling the stacked package. The secondary electronic component is positioned and connected within the substrate during the assembly process, which simplifies subsequent manufacturing steps and reduces overall complexity despite the additional component placement requirements.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent segments the package into distinct layers: substrate, secondary electronic component, and primary electronic component, with clear interfaces between them. This segmentation allows each component to be manufactured and prepared separately, then assembled through standardized processes, reducing the complexity of manufacturing the entire package as a single integrated structure.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS8836115B1Stacked inverted flip chip package and fabrication method

Publication Date: 2014.09.16 AMKOR TECH SINGAPORE HLDG PTE LTD

AI summary

A stacked inverted flip chip package includes a substrate having a secondary electronic component opening and first traces. Primary flip chip bumps electrically and physically couple a primary electronic component structure to the substrate. Secondary flip chip bumps electrically and physically couple an inverted secondary electronic component to the primary electronic component structure between the primary electronic component structure and the substrate and within the secondary electronic component opening. By placing the secondary electronic component between the primary electronic component structure and the substrate, the height of the stacked inverted flip chip package is minimized.