Inverted Gate Cut Structure for Lower Capacitance and Resistance
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Solution Overview
Problem
Conventional semiconductor IC devices face challenges in maintaining switching speeds and reducing current leakage as device dimensions shrink, leading to issues with parasitic capacitances and resistance characteristics due to the design of gate structures.
Innovation Solution
The introduction of an inverted gate cut region within the gate structure, which separates the gate into distinct sections, providing a larger top contact landing surface area and reducing parasitic capacitances by decreasing conductive material in the bottom perimeter region, thereby improving resistance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are shrunk to increase density, then device density is improved, but parasitic capacitances increase and switching speeds deteriorate
Solution Approach 1:
The gate structure is segmented into multiple sections by introducing gate cut regions that extend through the gate material. This segmentation divides the continuous gate into discrete segments, reducing the overall parasitic capacitance while maintaining the electrical connection through conductive material in the isolation layer.
Solution Approach 2:
An intermediary structure is introduced between the gate segments - a conductive material within the isolation layer that provides electrical connection between separated gate portions. This intermediary allows the gate to be physically segmented for reduced capacitance while maintaining electrical continuity for proper transistor operation.
2Object-affected harmful factors
If gate structure is modified to reduce parasitic capacitances, then parasitic capacitances are reduced, but resistance characteristics deteriorate
Solution Approach 1:
The isolation layer is configured with different local properties: regions beneath the gate segments contain conductive material for low resistance, while regions between gates contain insulating material for electrical isolation. This local differentiation allows simultaneous optimization of resistance and capacitance characteristics.
Solution Approach 2:
The gate cut regions are formed within the isolation layer structure, nesting the isolation function within the gate support infrastructure. The conductive material is nested within the isolation layer to provide both structural support and electrical connection pathways.
3Ease of manufacture
If conventional gate structures are used, then manufacturing is simpler, but switching performance and current leakage control deteriorate
Solution Approach 1:
The isolation layer with embedded conductive material is formed preliminarily before the gate material is deposited. This preliminary preparation of the isolation layer with pre-defined conductive pathways simplifies subsequent gate fabrication while ensuring proper electrical connections are already in place.
Data Source
AI summary
A semiconductor IC device includes an inverted gate cut region with a relatively larger bottom surface area compared to its top surface area. As a result, an associated gate structure may have a relatively larger top contact landing surface area relative to its bottom surface area. The increased landing area further enables the frontside contact to be in further perimeter locations. The inverted gate cut region also results in improved resistance characteristics through the gate structure. Specifically, the inverted gate cut region enables a wide region between a top channel and the inverted gate cut region that provides a relatively lower electrical resistance therethrough. Similarly, the inverted gate cut region causes a bottom perimeter region with decreased conductive material therein which advantageously results in lower associated parasitic capacitances.