Semiconductor Storage Cell Inverted Latch Circuit Design
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Solution Overview
Problem
Conventional semiconductor storage devices face challenges in achieving high-speed access while maintaining a small layout space, as existing tag memory technologies like SRAM and flip-flop based systems limit operating frequency and increase chip costs due to larger layout requirements.
Innovation Solution
A semiconductor storage device employing a first latch circuit and a storage cell with second latch circuits operating with inverted logic, allowing for high-speed data storage and retrieval without using flip-flops, resulting in a simpler configuration and reduced layout area, thus enabling cost-effective tag memory solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flip-flop based tag memory is used, then data storage reliability is improved, but layout area increases and operating frequency is limited
Solution Approach 1:
The patent inverts the conventional approach by using latch circuits instead of flip-flops for tag memory. Latch circuits operate with inverted logic levels, allowing them to achieve the same data storage function with smaller transistor count and reduced layout area while maintaining reliability through the complementary latch structure.
Solution Approach 2:
The patent extracts the essential data storage function from the complex flip-flop structure and implements it using simpler latch circuits. By removing unnecessary circuit elements and using only the core latching mechanism, the layout area is significantly reduced while preserving the data storage capability.
2Speed
If SRAM based tag memory is used, then data access speed is improved, but layout area increases and manufacturing cost increases
Solution Approach 1:
The patent replaces expensive SRAM cells with simpler, cheaper latch circuit structures. While SRAM offers fast access, the latch circuits achieve comparable speed for tag memory operations at a fraction of the area and cost, making them a more economical choice for this specific application.
Solution Approach 2:
The patent changes the operational parameters of the tag memory by using latch circuits that operate with inverted logic levels. This parameter change allows the circuit to achieve high-speed operation similar to SRAM while using significantly fewer transistors per storage element, thereby reducing layout area and manufacturing cost.
3Area of stationary object
If tag memory layout area is reduced, then chip cost is reduced, but data access speed may be limited
Solution Approach 1:
The patent introduces dynamic clocking and control signals to the latch circuits, enabling them to operate at high speeds despite the simplified structure. The dynamic operation allows the compact latch circuits to achieve data access speeds comparable to larger SRAM implementations, resolving the speed-area tradeoff.
Data Source
AI summary
A semiconductor storage device including a first latch circuit for latching stored data and a storage cell part including a plurality of second latch circuits that operate with inverted logic from the first latch circuit and receives the stored data from the first latch circuit to output the received data using the second latch circuit selected in accordance with a selection signal.