Inverted 3D Memory Stack Layout for Lower DRAM Thermal Resistance
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Solution Overview
Problem
Dynamic random-access memory (DRAM) die stacks face thermal challenges due to the large number of stacked semiconductor dice, which increase thermal resistance and hinder efficient heat dissipation from the bottom of the dice stack to the cooling solution at the top.
Innovation Solution
The configuration of DRAM dice in integrated circuit packages is modified by placing the digital device layer, which has higher power consumption and generates more heat, closer to the cooling solution, thereby reducing thermal resistance and improving heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple layers of DRAM dice are stacked to increase memory capacity, then memory storage capacity is improved, but thermal resistance increases and heat dissipation becomes more difficult
Solution Approach 1:
The patent inverts the conventional stack configuration by placing the high-power digital device layer (PHY layer with SerDes, address, read, write logic, output drivers) at the top of the stack closest to the cooling solution, rather than at the bottom. This inversion allows heat to be dissipated more efficiently from the highest power-generating layer directly to the cooling solution without having to travel through multiple DRAM layers, thereby resolving the thermal resistance problem while maintaining high memory capacity through vertical stacking
2Ease of manufacture
If the digital device layer is placed at the bottom of the stack to facilitate electrical connections, then ease of manufacture is improved, but heat dissipation deteriorates because the high-power circuitry is farthest from the cooling solution
Solution Approach 1:
The patent applies inversion by relocating the digital device layer from the bottom to the top of the stack, placing it adjacent to the cooling solution. This configuration prioritizes thermal management over manufacturing convenience, accepting that electrical connections must now route through the DRAM layers via through-silicon vias (TSVs), but achieving superior heat dissipation from the high-power circuitry
Solution Approach 2:
The patent utilizes the vertical dimension (z-axis) to optimize thermal pathways by stacking layers in a specific sequence with the digital device layer at the top. This dimensional arrangement creates a direct thermal pathway from the heat-generating digital circuits through the cooling solution, transforming the thermal management approach from horizontal to vertical heat flow
3Reliability
If the refresh rate is increased to ensure reliable operability at higher temperatures, then reliability is improved, but performance decreases and power overhead increases
Solution Approach 1:
The patent takes preliminary action by proactively managing heat dissipation through optimized stack configuration before thermal problems affect DRAM reliability. By placing the cooling solution adjacent to the digital device layer and optimizing thermal pathways, the system prevents temperature-induced reliability issues before they occur, eliminating the need for increased refresh rates and their associated performance penalties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the thermal resistance between the high-power circuitry and the cooling solution, maintaining lower operating temperatures for the memory layers and improving overall thermal management of the DRAM die stacks.
Implementation Method 1
heat dissipation from the bottom of the dice stack to the cooling solution at the top
Implementation Method 2
air cooled heat sink with fins, liquid cooling pipes
Data Source
AI summary
An integrated circuit die stack is disclosed that includes a digital device layer, an underlying layer, and a cooling solution. The underlying layer has a lower power consumption relative to the digital device layer. The digital device layer is disposed closer to the cooling solution. In another example, memory layers and a digital device layer are configured into a three-dimensional memory stack. The digital device layer has a first surface (side) located closest to a cooling solution and the memory layers are located on a second surface (side) of the digital device layer opposite to the first surface (side) thereof. The cooling solution is adapted to receive and dissipate heat from the digital device layer and the memory layers.