Inverted NAND String Architecture for Enhanced Data Retention
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Solution Overview
Problem
As semiconductor memory technologies, such as NAND flash memory, face challenges with increased variability in memory cell characteristics and reduced data retention and cycling endurance as process geometries shrink, there is a need for improved memory operations that enhance these aspects.
Innovation Solution
The use of inverted NAND strings, which include inverted floating gate transistors or charge trap transistors with a tunneling layer between the floating gate or charge trap and the control gate, allows for improved data retention and cycling endurance through optimized programming and erase operations, and can be oriented orthogonally above a substrate in a three-dimensional memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 2D NAND structures are used, then manufacturing process is simpler, but data retention time decreases and cycling endurance reduces as process geometries shrink
Solution Approach 1:
The patent transitions from conventional 2D planar NAND structures to vertically stacked 3D NAND structures. Multiple memory cell layers are stacked along the vertical axis, with bit lines extending through multiple layers. This dimensional change increases storage density while improving data retention and cycling endurance by reducing the impact of process geometry variations.
Solution Approach 2:
The patent implements a hierarchical structure where memory cell strings are nested within vertical wells, with multiple bit lines nested through different layers. Control gates are positioned above floating gates in an inverted configuration, creating nested functional layers that improve reliability while managing structural complexity.
2Quantity of substance
If process geometries are shrunk to increase density, then storage capacity increases, but variability in memory cell characteristics increases and cycling endurance decreases
Solution Approach 1:
By moving to vertical stacking, the patent achieves increased storage density without further shrinking horizontal process geometries. The vertical dimension provides additional scaling space, allowing maintenance of larger, more reliable transistor dimensions in the lateral direction while achieving higher density through multi-layer stacking.
Solution Approach 2:
The patent applies different structural configurations to different regions: inverted floating gate transistors in some layers, charge trap transistors in others, and varied bit line configurations. This allows optimization of local cell characteristics to reduce variability while maintaining overall high density.
3Reliability
If inverted NAND structures with tunneling layers are used, then data retention and cycling endurance improve, but manufacturing process complexity increases
Solution Approach 1:
The patent inverts the conventional NAND structure by positioning control gates above floating gates rather than below. This inversion enables direct tunneling between the control gate and floating gate through a thin oxide layer, facilitating efficient programming and erase operations while improving cycling endurance despite increased process complexity.
Solution Approach 2:
The patent modifies key structural parameters including introducing thin tunneling oxide layers (e.g., 5-10 nm), adjusting floating gate and control gate dimensions, and optimizing vertical spacing between layers. These parameter changes enable effective tunneling-based programming while managing manufacturing complexity through controlled process specifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Inverted NAND structures provide enhanced data retention times and improved programming and erase speeds compared to conventional 2D NAND structures, addressing the limitations of shrinking process geometries and variability in memory cell characteristics.
Implementation Method 1
The amount of charge on the floating gate is typically controlled using Fowler-Nordheim (F-N) tunneling or hot-electron injection
Implementation Method 2
The amount of charge on the floating gate is typically controlled using Fowler-Nordheim (F-N) tunneling or hot-electron injection
Data Source
AI summary
Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and erase verify operations. An inverted NAND string may include a string of inverted floating gate transistors or a string of inverted charge trap transistors. In one embodiment, an inverted floating gate transistor may include a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor. The arrangement of the tunneling layer between the floating gate and the control gate allows electrons to be added to or removed from the floating gate via F-N tunneling between the floating gate and the control gate. The inverted NAND string may be formed above a substrate and oriented such that the inverted NAND string is orthogonal to the substrate.