Inverted Power Device Chip Configuration for Parasitic Inductance Reduction
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Solution Overview
Problem
Power devices with parasitic inductors cause long switching times and high switching losses due to the long conductive path between the source terminal and leads, leading to delayed turning-off of the power transistor.
Innovation Solution
Reversing the chip configuration so that the source terminal faces the heat-sink, reducing the conductive path length and transforming it into a mainly resistive coupling, thereby enabling faster switching times and lower losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source terminal is connected to source leads through a long conductive path to meet safety parameters, then creepage and clearance distances are satisfied, but parasitic inductance increases causing long switching times
Solution Approach 1:
The chip is inverted so that the source terminal faces the mounting surface and connects directly to the heat-sink, while the drain terminal faces away. This inversion reverses the traditional connection topology, allowing the source lead to be extremely short and directly connected to the heat-sink, thereby minimizing parasitic inductance while still meeting safety parameters through appropriate lead arrangement.
2Reliability
If the source terminal is connected through a long conductive path, then safety distances are maintained, but parasitic inductance causes high switching losses
Solution Approach 1:
By inverting the chip configuration, the source terminal connects to the heat-sink through a minimal conductive path, reducing parasitic inductance. This reduction in parasitic inductance directly decreases the energy lost during switching operations, thereby reducing switching losses while maintaining safety distances through proper lead positioning.
3Reliability
If the source terminal connects to leads through extended path, then safety parameters are met, but turning-off delay increases due to parasitic inductor
Solution Approach 1:
The chip inversion places the source terminal in direct contact with the heat-sink, creating an extremely short connection path. This minimizes the parasitic inductance that causes delay during turn-off operations, enabling faster response when the power transistor needs to be switched off, while safety parameters are satisfied through appropriate lead arrangement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in extremely short switching times and low switching losses without significant changes to the existing power device or production process, while maintaining compliance with safety parameters.
Implementation Method 1
an electrically conductive heat-sink connected to said at least one chip for dissipating the heat generated by said at least one electronic component towards the mounting surface
Data Source
AI summary
An electronic device includes at least one electronic component chip having a first conduction terminal and a control terminal on a first surface of the chip and a second conduction terminal on a second surface opposite the first surface of the chip. An insulating body embeds the chip. The insulating body includes a mounting surface and an electrically conductive heat-sink connected to the first conduction terminal on the first surface of the chip, but insulated from the control terminal. An opening in a first surface of the insulating body exposes a surface of the electrically conductive heat sink. The electrically conductive heat sink includes a perimeter cavity configured for alignment with an encircling configuration of the control terminal, wherein the perimeter cavity contains a material that insulates the control terminal from the heat sink.