Self-aligned gate caps with inverted profile for transistor isolation
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Solution Overview
Problem
Conventional field-effect transistor structures face yield loss due to the risk of electrical shorting between the metal gate and self-aligned contacts, primarily caused by the proximity of conformal metal gate layers to the contacts.
Innovation Solution
A structure and method involving a gate structure with a work function metal layer, a first conductor layer, and a second conductor layer, where the first conductor layer is recessed relative to the second conductor layer, and a dielectric cap is formed with sections over the top surface and adjacent to the sidewalls, enhancing electrical isolation and reducing the risk of shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conformal metal gate layers are placed close to self-aligned contacts, then device integration density is improved, but electrical shorting risk between gate and contact increases
Solution Approach 1:
A dielectric cap layer is introduced as an intermediary between the metal gate structure and the self-aligned contact. This cap layer is conformally deposited over the metal gate and extends laterally to cover the contact region, providing electrical isolation while allowing the contact to be formed through the dielectric cap. The intermediary dielectric material prevents direct electrical contact between the conductive gate and contact layers, eliminating the shorting risk while maintaining close proximity for high integration density.
Solution Approach 2:
The solution transitions from a planar two-dimensional layout to a three-dimensional stacked structure. The metal gate is recessed relative to the contact, and a dielectric cap is deposited conformally over the gate structure, creating vertical layering. This dimensional change allows the gate and contact to be in close horizontal proximity while maintaining vertical electrical isolation through the dielectric cap, effectively resolving the contradiction between integration density and electrical isolation.
2Reliability
If metal gate layers are recessed relative to contact layers, then electrical isolation is improved, but manufacturing complexity increases
Solution Approach 1:
The metal gate layers are recessed relative to the contact layers before the dielectric cap is deposited. This preliminary action creates the necessary topography for the subsequent conformal dielectric deposition, ensuring that the dielectric cap will cover both the gate structure and the contact region. By performing the recess operation beforehand, the manufacturing process establishes the correct spatial relationships early, simplifying later steps and reducing overall complexity despite the additional recess operation.
Solution Approach 2:
The conductor layers are divided into multiple segments: a first conductor layer forming the metal gate and a second conductor layer forming the contact. These segments are separated vertically and horizontally, with the first conductor layer recessed relative to the second. This segmentation allows independent formation and positioning of gate and contact structures, enabling precise control over their relative positions and simplifying the manufacturing process by treating them as separate entities rather than a single integrated structure.
Data Source
AI summary
Structures for a field-effect transistor and methods of forming a structure for field-effect transistor. A gate structure includes a work function metal layer, a first conductor layer, and a second conductor layer arranged over the work function metal layer. The second conductor layer has a sidewall and a top surface, and the first conductor layer has a first section arranged between the second conductor layer and the work function metal layer and a second section arranged adjacent to a first portion of the sidewall of the second conductor layer. A dielectric cap is arranged on the gate structure. The dielectric cap has a first section arranged over the top surface of the second conductor layer and a second section arranged adjacent to a second portion of the sidewall of the second conductor layer.


