Inverted Subpixel Wiring Layout for Low-RC Display Panels
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Solution Overview
Problem
Existing display devices face challenges in minimizing RC delay of data lines, preventing twisting and short-circuits between wires, and maximizing the opening ratio while managing increased connection lines, which affect the performance and repairability of display panels.
Innovation Solution
The display device is designed with a specific arrangement of subpixels and connection lines, including non-inverted and inverted structures, symmetrical and pseudosymmetrical data connections, and separate wiring layers to minimize RC delay, prevent short-circuits, and enhance aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of connection lines is increased to provide more data lines for subpixels, then the aperture ratio is reduced due to more wires occupying space, but the data transmission capability is improved
Solution Approach 1:
The patent transitions from planar 2D arrangement of data lines to a 3D stacked configuration where data lines are arranged in multiple layers (first data line in first layer, second data line in second layer). This vertical stacking allows more data lines to coexist without increasing the horizontal wire density, thereby maintaining aperture ratio while increasing data transmission capability.
Solution Approach 2:
The patent implements nested connection structures where connection electrodes are positioned between the first and second data lines, and additional connection lines are integrated within the stacked configuration. This nesting allows multiple connection paths to be packed into the same spatial footprint, increasing functional capacity without proportionally increasing the area occupied by wires.
2Quantity of substance
If more connection lines are added to increase data transmission capacity, then the reliability decreases due to increased risk of twisting and short-circuits between wires
Solution Approach 1:
By arranging data lines in vertical layers rather than horizontal planes, the patent reduces the probability of wire twisting and short-circuits. The stacked configuration (first data line in first layer, second data line in second layer) physically separates connection paths in the vertical dimension, minimizing interference and contact risks between lines.
Solution Approach 2:
The patent divides the connection structure into segmented layers with distinct functional zones. Connection electrodes are positioned in the space between data lines, and insulation layers are strategically placed to segment and isolate different conductive elements. This segmentation reduces the complexity of wire routing and minimizes opportunities for short-circuits.
3Ease of manufacture
If the data lines are arranged in a conventional linear fashion, then the manufacturing is simpler, but the RC delay increases due to longer wire paths
Solution Approach 1:
The patent reduces RC delay by transitioning from linear horizontal routing to vertical stacked routing. The first data line and second data line are positioned in different layers, allowing shorter connection paths between subpixels and data lines. This 3D arrangement decreases the total wire length and reduces capacitive loading, thereby reducing RC delay while remaining compatible with standard semiconductor manufacturing processes.
Data Source
AI summary
Disclosed is a display device including a first pixel including three subpixels respectively connected to first to third data lines arranged in a first direction and connected to a first gate line arranged in a second direction, a second pixel including three subpixels respectively connected to the first to third data lines and connected to a second gate line, a third pixel including three subpixels respectively connected to the first to third data lines and connected to a third gate line, and a fourth pixel including three subpixels respectively connected to the first to third data lines and connected to a fourth gate line, wherein emission areas and circuit areas included in the first pixel and the fourth pixel are inverted compared to emission areas and circuit areas included in the second pixel and the third pixel.