Hetero-structured Inverted-T Fin Transistor for Short Channel Effects
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Solution Overview
Problem
Conventional Fin-FET devices are optimized for either PMOS or NMOS devices due to their single material and orientation, leading to suboptimal performance for the other type, resulting in inadequate control of the channel region and increased susceptibility to short channel effects.
Innovation Solution
A method of forming hetero-structured, inverted-T fin structures using layers of semiconductor materials with different carrier mobilities, where a first layer provides high mobility to one carrier type and a second layer, etched to form inverted-T shapes, provides high mobility to the opposite carrier type, allowing for improved control and immunity to short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional Fin-FET structures use a single material and orientation optimized for one carrier type, then high drive current is achieved for either PMOS or NMOS, but performance is suboptimal for the other device type
Solution Approach 1:
The channel structure is segmented into multiple distinct regions: a first channel region with a first material orientation optimized for one carrier type, and a second channel region with a second material orientation optimized for the opposite carrier type. This segmentation allows each region to be independently optimized for its intended carrier type while functioning within the same transistor device.
Solution Approach 2:
Different portions of the channel structure are assigned different material properties and orientations tailored to local requirements. The first channel region uses a material orientation that provides high mobility for electrons (NMOS optimization), while the second channel region uses a different material orientation that provides high mobility for holes (PMOS optimization).
2Ease of manufacture
If conventional Fin-FET structures are used, then processing and materials remain consistent with previous technology nodes, but control of the channel region is inadequate leading to short channel effects
Solution Approach 1:
The channel structure transitions from a conventional planar two-dimensional configuration to a three-dimensional multi-region structure with vertical and lateral variations in material composition and orientation. This dimensional enhancement provides additional control mechanisms over the channel while maintaining compatibility with existing fabrication processes.
3Reliability
If multi-directional control of the channel is implemented, then immunity to short channel effects increases, but device structure complexity increases
Solution Approach 1:
The channel structure employs asymmetric material orientations where the first channel region has a crystal orientation optimized for electron transport while the second channel region has a different crystal orientation optimized for hole transport. This asymmetric design provides multi-directional control capabilities while maintaining a relatively straightforward fabrication approach.
Data Source
AI summary
The present invention provides a method of forming a transistor. The method includes forming a first layer of a first semiconductor material above an insulation layer. The first semiconductor material is selected to provide high mobility to a first carrier type. The method also includes forming a second layer of a second semiconductor material above the first layer of semiconductor material. The second semiconductor material is selected to provide high mobility to a second carrier type opposite the first carrier type. The method further includes forming a first masking layer adjacent the second layer and etching the second layer through the first masking layer to form at least one feature in the second layer. Each feature in the second layer forms an inverted-T shape with a portion of the second layer.