Inverted-T Floating Gate Memory Structure
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Solution Overview
Problem
The development of nonvolatile memory systems has led to incompatible memory card standards, and existing memory array architectures face challenges such as short channel effects and limited space for control gates and interlayer dielectric, which affect coupling efficiency and scalability.
Innovation Solution
The use of inverted-T shaped floating gates in nonvolatile memory arrays, formed using an etch stop layer between base and stem polysilicon layers, allows for improved coupling to the channel, reduces short channel effects, and provides additional space for control gates and interlayer dielectric, enabling better scalability and compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional floating gate structures are used, then manufacturing is simpler, but coupling efficiency to the channel is insufficient and short channel effects occur
Solution Approach 1:
The floating gate is designed with an asymmetric inverted-T shape where the base portion has a larger width than the stem portion. This asymmetric geometry provides broader coupling to the channel region at the base while maintaining a narrower profile at the stem to reduce short channel effects, directly resolving the contradiction between coupling efficiency and short channel effects.
Solution Approach 2:
The floating gate structure is segmented into two distinct portions: a base portion and a stem portion. This segmentation allows each portion to serve different functions - the base portion optimizes channel coupling while the stem portion minimizes short channel effects, enabling both improved reliability and controlled complexity.
2Reliability
If wider floating gates are used to improve channel coupling, then coupling efficiency increases, but space for control gates and interlayer dielectric is reduced
Solution Approach 1:
The inverted-T shape creates an asymmetric distribution of floating gate width - wide at the base for channel coupling and narrow at the stem for spacing. This allows the structure to achieve good channel coupling without occupying excessive horizontal space that would interfere with control gates and interlayer dielectric.
Solution Approach 2:
The floating gate structure transitions from a conventional planar shape to a three-dimensional inverted-T shape with vertical extent. This dimensional change allows the base portion to extend laterally for coupling while the stem portion extends vertically, effectively utilizing the third dimension to resolve the space conflict.
3Area of stationary object
If narrower floating gates are used to provide space for control gates, then space availability increases, but coupling efficiency and surface area for word line coupling are reduced
Solution Approach 1:
The inverted-T shape utilizes vertical dimension to provide coupling surface area. The stem portion extends upward from the base, providing adequate surface area for word line coupling in the vertical direction while maintaining a narrow profile in the horizontal direction to accommodate control gates and interlayer dielectric.
Data Source
AI summary
Floating gates of a floating gate memory array have an inverted-T shape in both the bit line direction and the word line direction. Floating gates are formed using an etch stop layer that separates two polysilicon layers that form floating gates. Word lines extend over floating gates in one example, and word lines extend between floating gates in another example.