Inverted-T Floating Gate Reduces Coupling in Flash Memory
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Solution Overview
Problem
In non-volatile flash memory systems, there is a challenge in maximizing the coupling between floating gates and control gates while minimizing the coupling between adjacent floating gates, which is essential for efficient data storage and retrieval, especially as memory cell sizes are reduced to increase storage density.
Innovation Solution
The implementation of inverted-T shaped floating gates, where a narrower upper floating gate portion increases the coupling with the control gate without increasing the substrate area, and a self-aligned process is used to form these gates, reducing capacitive coupling between adjacent floating gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory cell size is reduced to increase storage density, then the storage capacity per unit area is improved, but the coupling between adjacent floating gates increases causing interference
Solution Approach 1:
The floating gate is designed with an inverted-T shape, creating an asymmetric structure where the upper portion is narrower than the lower portion. This asymmetry reduces the overlapping area between adjacent floating gates, thereby minimizing capacitive coupling and interference while maintaining adequate coupling with the control gate.
Solution Approach 2:
The invention transitions from a conventional rectangular floating gate to a three-dimensional inverted-T shape with different widths at different heights. By varying the cross-sectional dimensions vertically, the design achieves reduced lateral coupling between adjacent cells while preserving vertical coupling with the control gate.
2Productivity
If the coupling between floating gates and control gates is maximized, then the data storage efficiency is improved, but the coupling between adjacent floating gates also increases
Solution Approach 1:
The inverted-T shape creates asymmetric coupling characteristics: the narrow upper portion minimizes coupling with adjacent floating gates, while the lower portion maintains adequate coupling with the control gate through the tunnel dielectric layer, achieving selective coupling optimization.
Solution Approach 2:
Different portions of the floating gate are given different widths to serve different functions: the upper narrow portion reduces interference with neighbors, while the lower wider portion ensures sufficient coupling with the control gate for effective programming and reading operations.
3Manufacturing precision
If a self-aligned process is used to form floating gates, then the manufacturing precision is improved, but the process complexity increases
Solution Approach 1:
The method forms the inverted-T shaped floating gate through a sequential self-aligned process where masking portions and sidewall spacers are deposited and patterned in specific sequences. Each step automatically aligns features without requiring additional alignment operations, achieving high precision through pre-planned process sequencing.
Solution Approach 2:
The self-aligned process utilizes the deposited masking portions and sidewall spacers to automatically define the positions of subsequent features. The structure itself serves as the alignment reference for the next processing step, eliminating the need for external alignment mechanisms and reducing process complexity despite multiple deposition steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the coupling between floating and control gates, allowing for improved data storage density and reduced interference between adjacent floating gates, enabling more efficient and scalable memory cell architecture.
Implementation Method 1
enhances the coupling between floating and control gates
Implementation Method 2
reduced capacitive coupling between adjacent floating gates
Data Source
AI summary
A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.