Inverted Transistor Fabrication Reducing Stray Capacitance
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Solution Overview
Problem
Current methods for fabricating field effect devices are complex and result in devices with suboptimal electric performance due to high stray capacitances, which are difficult to reduce effectively.
Innovation Solution
A method involving a substrate with a dividing pattern and semiconductor material pattern, where a gate pattern defines source and drain regions, and cap layers are used to release these regions, allowing for the formation of access vias and lateral spacers to reduce capacitance, along with selective epitaxy to improve semiconductor material quality and reduce capacitance further.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source and drain contacts are placed on one side of the semiconductor film to reduce stray capacitances, then electric performance is improved, but fabrication complexity increases due to amorphization requirements and optical property-based mask alignment
Solution Approach 1:
The substrate is divided into multiple sections using a dividing pattern that creates distinct regions for source, drain, and conduction channel. This segmentation allows independent processing and simplifies the overall fabrication by breaking down the complex inverted transistor structure into manageable segments that can be fabricated using standard techniques.
Solution Approach 2:
The patent applies inversion by placing the gate electrode on the opposite side of the semiconductor film from the source and drain contacts, creating an inverted transistor architecture. This inversion reduces the facing surface between gate and contacts, thereby reducing stray capacitances and improving electric performance while maintaining fabrication simplicity through the dividing pattern approach.
2Ease of manufacture
If conventional fabrication methods are used, then manufacturing process is simpler, but stray capacitances remain high reducing device performance
Solution Approach 1:
The patent transitions from a planar transistor architecture to a three-dimensional inverted architecture where the gate electrode is positioned on the opposite side of the semiconductor film from the source and drain contacts. This dimensional change reduces the overlapping area between gate and contacts, thereby reducing stray capacitances and improving electric performance while maintaining ease of manufacture through the dividing pattern approach.
3Device complexity
If epitaxy is performed from support substrate to form source and drain regions, then device structure is created, but fabrication becomes very difficult and final device performance does not meet expectations
Solution Approach 1:
The dividing pattern is formed on the substrate before any other fabrication steps. This preliminary action establishes the geometric framework for the inverted transistor, defining the locations of source, drain, and conduction channel regions. By pre-defining these regions, subsequent fabrication steps become simpler and more straightforward, avoiding the complexity of forming structures through epitaxy from a support substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the fabrication process while improving electric performance by reducing stray capacitances and enabling better quality epitaxy, leading to enhanced device performance.
Implementation Method 1
The gate electrode acts as etch mask for etching the layer of semiconductor on insulator
Implementation Method 2
Epitaxy is performed from the support substrate to connect the support substrate with the layer of semiconductor on insulator. The epitaxied regions form the source and drain regions.
Implementation Method 3
depositing a cap layer so as to cover the substrate, the semiconductor material pattern and the gate pattern
Implementation Method 4
It is also possible to provide for a chemical mechanical polishing step of the second cap layer configured to release the delineation patterns.
Data Source
AI summary
A SOI substrate is covered by a semiconductor material pattern which includes a dividing pattern made from electrically insulating material. The dividing pattern is coated by one or more semiconductor materials. The semiconductor material pattern is covered by a gate electrode which is facing the dividing pattern. The semiconductor material pattern and the gate pattern are covered by a cap layer. The substrate is eliminated to access the source/drain regions. Two delineation patterns are formed to cover the source region and drain region and to leave the dividing pattern free. A second cap layer is deposited and access vias are formed to access the source/drain regions by elimination of the delineation patterns.