Inverted Trapezoid Active Areas for Contact and Isolation Scaling

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Solution Overview

Problem

As semiconductor structures become more integrated, the reduced size of transistor structures leads to poor contact between the storage node plug and the transistor, affecting performance and potentially causing device failure.

Innovation Solution

A method involving the formation of inverted trapezoid-shaped trenches in a mask layer, followed by filling these with an epitaxy layer to create active areas and then forming regular trapezoid-shaped trenches between these areas, which are filled with a dielectric layer to create an isolation structure, ensuring a large contact area and effective isolation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the integration level of the semiconductor structure is increased, then the size of the transistor structure is reduced, but the contact area between the storage node plug and the transistor becomes smaller resulting in poor contact

Engineering Contradiction:
Improveintegration levelVSAvoidcontact quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Instead of reducing the contact area proportionally with transistor size reduction, the patent inverts the approach by creating an enlarged contact area through inverse trapezoidal trench structures. The trench width at the upper end is greater than at the lower end, allowing the storage node plug to contact the active area at a larger upper surface area while the transistor size is reduced, thus improving contact quality despite higher integration levels

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent addresses the contact area problem by transitioning from a two-dimensional planar contact to a three-dimensional inverted trapezoidal structure. The trench extends vertically into the substrate with varying width, creating additional contact surface area in the vertical dimension that compensates for the reduced planar footprint, thereby maintaining reliable contact at higher integration levels

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the active area contact area is increased to improve contact quality, then the contact between storage node plug and transistor is improved, but the device size increases

Engineering Contradiction:
Improvecontact qualityVSAvoiddevice size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The inverse trapezoidal trench structure is nested within the existing transistor structure footprint. The trench extends downward into the substrate rather than expanding outward at the surface, allowing the contact area to be increased vertically without increasing the horizontal device footprint, thus maintaining compact device size while improving contact quality

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent resolves the size conflict by moving the contact area expansion from the horizontal plane to the vertical dimension. The inverted trapezoidal trench creates additional contact surface area through its depth and varying width profile, enabling improved contact quality without increasing the device's planar dimensions

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enhances the electrical performance and reliability of semiconductor structures by ensuring good contact between active areas and structures, while maintaining a strong isolation effect without increasing the substrate's size, thus improving the overall performance and reducing power consumption.

Implementation Method 1

An etching process is performed to form a plurality of first trenches in the mask layer

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

An epitaxy layer is formed on the substrate. The epitaxy layer is filled in each of the first trenches to form an active area

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 3

A dielectric layer is filled in the second trench to form an isolation structure

Methodology Applied
Scientific EffectDielectric isolation: Dielectric

Data Source

PatentUS12557616B2Method for manufacturing semiconductor structure with active area having inverted trapezoid cross-sectional shape, and semiconductor structure with active area having inverted trapezoid cross-sectional shape
Publication Date: 2026.02.17 CHANGXIN MEMORY TECH INC
  • US12557616B2 patent drawing
  • US12557616B2 patent drawing
  • US12557616B2 patent drawing

AI summary

A method for manufacturing a semiconductor structure includes operations as follows. A substrate is provided, and a mask layer is formed on the substrate. An etching process is performed to form a plurality of first trenches in the mask layer, where the first trench has an inverted trapezoid cross-sectional shape. An epitaxy layer is formed on the substrate, where the epitaxy layer is filled in each of the first trenches to form an active area. The mask layer is removed to form a plurality of second trenches, where the second trench is arranged between adjacent active areas, and the second trench has a regular trapezoid cross-sectional shape. A dielectric layer is filled in the second trench to form an isolation structure.