Inverted Trapezoid Dummy Patterns for Semiconductor Gate Fabrication
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Solution Overview
Problem
Conventional methods for fabricating semiconductor devices with high dielectric constant gate layers suffer from leakage current and threshold voltage issues due to poor metal gap fill in trench structures, leading to voids and reliability problems.
Innovation Solution
An ion implantation process is performed on a polysilicon layer to create dummy patterns with a narrower neck than top, enhancing etching rates and improving metal gap fill by forming trenches with a wide opening, thereby reducing void formation and increasing device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If conventional etching process is used to form dummy patterns, then the dummy patterns are shaped into trapezoids with narrow top and wide bottom, but this results in poor metal gap fill and void formation in the trench structures
Solution Approach 1:
The patent applies asymmetry by inverting the conventional trapezoidal dummy pattern shape. Instead of narrow-top wide-bottom trapezoids, the invention creates inverted trapezoids with wide top and narrow bottom. This asymmetric shape change allows better metal layer deposition by providing a wider opening for sputtering while maintaining adequate trench coverage, thereby eliminating void formation and improving metal gap fill quality.
Solution Approach 2:
The patent directly inverts the conventional dummy pattern geometry. Rather than forming trapezoids that narrow toward the top, the invention creates dummy patterns that widen toward the top (inverted trapezoids). This inversion reverses the problematic narrow-opening effect and creates favorable geometry for subsequent metal deposition processes, solving the poor metal gap fill issue.
2Manufacturing precision
If the opening is narrowed after dummy pattern removal, then the trench structure is formed, but this causes poor metal gap fill effect and overhang problems during sputtering
Solution Approach 1:
The inverted trapezoidal shape creates asymmetric geometry where the opening width differs from the bottom width. This asymmetry is deliberately designed to favor the deposition process: the wider top opening facilitates metal layer deposition and prevents overhang, while the narrower bottom maintains precise trench definition. The asymmetric shape resolves the conflict between trench precision and deposition ease.
Solution Approach 2:
The patent changes the geometric parameters of the dummy patterns by inverting their shape. Specifically, it alters the width-to-height ratio and the profile angle to create inverted trapezoids. This parameter change transforms the opening geometry from narrow to wide, fundamentally improving the metal deposition process while maintaining trench formation precision through controlled etching parameters.
3Ease of manufacture
If silicon oxide is used as gate dielectric layer material, then the conventional dielectric material is applied, but leakage current occurs when thickness is reduced
Solution Approach 1:
The patent employs composite materials by combining multiple dielectric layers with different properties. Instead of using a single silicon oxide layer, the invention creates a stacked structure comprising silicon oxide layers interspersed with silicon nitride barrier layers. This composite dielectric structure maintains manufacturability through standard deposition processes while effectively preventing leakage current through the low-permeability silicon nitride barriers, thus resolving the contradiction between ease of manufacture and leakage control.
Solution Approach 2:
The patent applies local quality by introducing silicon nitride barrier layers at specific locations within the gate dielectric stack. Rather than uniformly changing the entire dielectric structure, the invention places low-permeability silicon nitride layers locally at critical interfaces and within the oxide stack. This localized application of different material properties prevents leakage current paths while maintaining the overall silicon oxide dielectric structure's manufacturability and electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively enhances the reliability and performance of semiconductor devices by improving metal gap fill and reducing voids in trench structures, maintaining device integrity and performance.
Implementation Method 1
an ion implantation process is performed after the polysilicon layer is formed so as to dope an N-type dopant into the polysilicon layer
Implementation Method 2
when removing a portion of the polysilicon layer, different etching rates at different depth locations of the doped polysilicon layer are utilized
Implementation Method 3
when the opening is filled with the metal layer by a sputtering process
Data Source
AI summary
A method for fabricating a semiconductor device is described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between adjacent dummy patterns, and the top of each dummy pattern is exposed. Thereafter, the dummy patterns are removed to form a plurality of trenches in the dielectric layer. A plurality of gate structures is formed in the trenches, respectively.