Inverter-Based ADC Compensation for Fast Low-Power Conversion
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Solution Overview
Problem
Conventional Analog to Digital Converters (ADCs) face challenges in achieving high dynamic range and low power consumption, particularly in wireless and wireline communications, where they consume a significant portion of the power and exhibit high conversion latency, making them inefficient for modern communication systems.
Innovation Solution
The development of an inverter-based ADC with a dynamic discrete time architecture that uses a pre-charge circuit to reduce power consumption, employs a multi-bit flash comparator with time interleaving and temperature and voltage compensation, and incorporates error detection and correction mechanisms to enhance manufacturing yield and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional ADC architectures are used to achieve high conversion rates, then conversion speed is improved, but power consumption increases significantly
Solution Approach 1:
The ADC is divided into multiple sub-ADCs operating in parallel with time-interleaved architecture. Each sub-ADC handles a portion of the conversion tasks, allowing the system to achieve high conversion rates without requiring a single high-power converter, thus distributing power consumption across multiple lower-power units
Solution Approach 2:
The patent employs periodic sampling and time-interleaved conversion cycles where multiple sub-ADCs take turns converting different portions of the input signal. This periodic operation allows each sub-ADC to operate at lower instantaneous power levels while maintaining high overall conversion throughput through coordinated timing
2Speed
If device scaling is used to implement analog functions with minimum channel length, then transition frequency and operation speed are improved, but linearity and other analog parameters deteriorate
Solution Approach 1:
The patent adjusts critical device parameters such as channel length, width, and oxide thickness to optimize the balance between speed and linearity. By carefully selecting and tuning these parameters, the design achieves high transition frequency while maintaining acceptable linearity performance in ultra-deep submicron CMOS technology
Solution Approach 2:
The patent employs composite device structures combining different transistor types (NMOS and PMOS) in complementary configurations. This composite approach leverages the strengths of each device type to achieve both high-speed operation and improved linearity that cannot be obtained with single-device scaling alone
3Measurement precision
If high dynamic range is achieved in ADCs for wireless communications, then signal fidelity is improved, but power consumption increases to almost one-third or more of total available power
Solution Approach 1:
The high dynamic range conversion is segmented across multiple sub-ADCs with different gain settings and resolution levels. This segmentation allows the system to achieve high overall dynamic range by combining the outputs of multiple lower-power, lower-range converters rather than using a single high-power, high-range converter
Solution Approach 2:
The patent implements dynamic element matching and time-varying gain control where the ADC architecture adapts its configuration based on input signal conditions. This dynamic operation allows the system to achieve high dynamic range only when needed, reducing power consumption during operations with lower dynamic range requirements
Data Source
AI summary
A plurality of devices of a circuit perform a function associated with the circuit. A compensation module obtains a temperature value and/or core voltage value associated with the circuit and uses the temperature value and/or the core voltage value to adjust at least one device of the plurality of devices. The adjustment may include using one or more source resisters connected to the at least one device of the plurality of devices to adjust a device voltage threshold. The plurality of devices may perform analog to digital conversion, and the compensation module may generate a digital offset value using the temperature value and/or the core voltage value and add or subtract the digital offset value from an unadjusted digital output value to compensate for a change in the temperature value and/or the core voltage value.