Inverter-Based ADC Architecture for Low-Power High Dynamic Range
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Solution Overview
Problem
Conventional Analog to Digital Converters (ADCs) face challenges in achieving high dynamic range and low power consumption, particularly in wireless and wireline communication systems, where they consume a significant portion of the total available power and exhibit high conversion latency.
Innovation Solution
The design introduces an inverter-based ADC with a dynamic discrete time architecture, using NMOS and PMOS devices to reduce power consumption by only connecting the input signal to the NMOS devices after an output pre-charge cycle, and employs a multi-bit flash comparator with temperature and voltage compensation to optimize device selection and error correction, thereby enhancing manufacturing yield and reducing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional ADC architectures are used to achieve high conversion rates, then conversion speed is improved, but power consumption increases significantly
Solution Approach 1:
The ADC is divided into multiple independent flash comparator modules that operate in parallel, each handling a portion of the conversion task. This segmentation allows the system to achieve high conversion rates through parallel processing while each module consumes less power individually, reducing total power consumption compared to a single large-scale converter
Solution Approach 2:
The ADC employs time-interleaved operation where multiple flash comparators process different time slots of the input signal. By periodically switching between comparators and using pre-charge cycles, the system maintains high effective conversion rates while reducing instantaneous power consumption through distributed timing of operational events
2Productivity
If device scaling is applied to reduce cost and improve transition frequency, then manufacturing cost and operation speed are improved, but linearity and other analog parameters deteriorate
Solution Approach 1:
The system incorporates on-chip temperature and voltage sensors that automatically monitor operating conditions and feed back to the compensation module. This self-service mechanism enables real-time adaptation to process variations and environmental changes, maintaining high linearity despite device scaling effects without requiring external calibration equipment
Solution Approach 2:
The ADC dynamically adjusts operating parameters including bias currents, reference voltages, and comparator thresholds based on measured temperature and voltage conditions. By changing these parameters in response to environmental variations, the system compensates for scaling-induced parameter drift and maintains consistent linearity performance across different manufacturing batches and operating conditions
3Measurement precision
If high dynamic range is achieved in ADCs, then signal fidelity is improved, but power consumption increases
Solution Approach 1:
The high dynamic range requirement is divided among multiple flash comparator modules, each optimized for specific signal amplitude ranges. By segmenting the conversion task across parallel modules with different resolution capabilities, the system achieves overall high dynamic range while each module operates at lower power levels appropriate to its specific function
Solution Approach 2:
The system uses more flash comparators than the minimum required for the target resolution, with some comparators operating in a time-interleaved fashion. This excessive action provides redundancy and improved signal-to-noise ratio for enhanced dynamic range, while the time-multiplexed operation ensures that not all comparators consume full power simultaneously, balancing performance with power efficiency
Data Source
AI summary
Methods and systems are provided for circuits. One method is for increasing device threshold voltage distribution of a plurality of devices of a circuit. The method includes adjusting a device threshold voltage of the plurality of devices by different amounts; and selecting a subset of the plurality of devices with adjusted device threshold voltage by a device selection module for performing a function associated with the circuit. In one aspect, a system for device threshold voltage adjustment is provided. The system includes a sensor module for sensing one or more of temperature and voltage values of a die having a plurality of devices for a circuit; and a threshold temperature and voltage compensation module for receiving an input value from the sensor module to compensate variation in a device threshold voltage caused by changes of one or more of temperature and voltage of the die.