Inverter-Based ADC Architecture for High-Speed Low-Power Conversion
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Solution Overview
Problem
Conventional Analog to Digital Converters (ADCs) face challenges in achieving high dynamic range, low power consumption, and low cost, especially in ultra-deep submicron CMOS technology, due to high power consumption and conversion latency, which is undesirable for modern wireless and wireline communication systems.
Innovation Solution
The design employs an inverter-based ADC with a dynamic discrete time architecture, using NMOS and PMOS devices to reduce power consumption by only activating NMOS devices after an output pre-charge cycle, and incorporates a sample and hold circuit with programmable DC level shift and dynamic digital inverters, along with temperature and voltage compensation to optimize device selection and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional ADC architectures are used to achieve high conversion rates, then conversion speed is improved, but power consumption increases significantly
Solution Approach 1:
The patent implements a dynamic discrete time architecture where NMOS devices are activated only after an output pre-charge cycle, creating periodic operation patterns that reduce average power consumption while maintaining high conversion rates through efficient timing sequences
Solution Approach 2:
The patent employs dynamic digital inverters and sample and hold circuits with programmable DC level shift that adapt their operation based on input conditions, enabling the system to optimize between speed and power consumption dynamically rather than operating at fixed parameters
2Ease of manufacture
If device scaling is used to lower cost and improve digital logic performance, then manufacturing cost is reduced, but analog design parameters such as linearity and dynamic range are adversely affected
Solution Approach 1:
The patent incorporates temperature and voltage compensation mechanisms that dynamically adjust operating parameters to counteract the adverse effects of device scaling on analog performance, maintaining linearity and dynamic range despite using scaled transistors with minimum channel length and oxide thickness
3Measurement precision
If high dynamic range is achieved in ADCs, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent divides the conversion process into multiple stages using a dynamic discrete time architecture with segmented processing of analog inputs through sample and hold circuits and multi-stage digital inversion, achieving high dynamic range through cumulative precision while distributing power consumption across time-separated operations
Data Source
AI summary
Methods and devices are provided for circuits. One device includes an adjustment circuit having an adjustable resistor for modifying a resistance value of a resistive device, the adjustment circuit connected to an adjustment terminal of the resistive device. The resistance value of the adjustable resistor changes, when a voltage or charge on the adjustment terminal of the adjustable resistor is changed. The adjustable resistor is a phase change element with an adjusting terminal to which different voltage values are applied for adjusting a conversion device threshold value.