Inverter-Based ADC Threshold Compensation for Low-Power Conversion
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Solution Overview
Problem
Conventional Analog to Digital Converters (ADCs) face challenges in achieving high dynamic range and low power consumption, particularly in wireless and wireline communications, where they consume a significant portion of the total available power and exhibit high conversion latency.
Innovation Solution
The design introduces an inverter-based ADC with a dynamic discrete time architecture, using NMOS and PMOS devices to reduce power consumption by connecting the input signal to the NMOS devices only after an output pre-charge cycle, and employs a thermometer-to-binary encoding scheme with temperature and voltage compensation to optimize device selection and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional ADC architectures are used to achieve high conversion rates, then conversion speed is improved, but power consumption increases significantly
Solution Approach 1:
The patent implements a dynamic discrete-time architecture where the ADC operates in periodic phases (sampling phase and conversion phase) rather than continuously. During the sampling phase, the input signal is connected to NMOS devices only after an output pre-charge cycle, dynamically controlling when power-consuming operations occur. This dynamic operation reduces average power consumption while maintaining high conversion rates through efficient time-multiplexed operation.
Solution Approach 2:
The ADC employs periodic sampling and conversion cycles with distinct phases. The pre-charge cycle periodically resets the output before each conversion phase, creating a rhythmic operation pattern. This periodic action allows the system to achieve high conversion rates through efficient cycling while reducing power consumption by keeping devices in low-power states between active phases.
2Speed
If device scaling is used to implement analog functions with minimum channel length, then transition frequency and operation speed are improved, but linearity and other analog parameters deteriorate
Solution Approach 1:
The patent changes the operating parameters of scaled devices by implementing a discrete-time architecture with periodic pre-charge cycles and controlled sampling phases. This approach compensates for the reduced linearity of scaled devices by operating them in specific regimes where their high transition frequency is leveraged while minimizing the impact of scaling-induced non-linearity through careful timing and signal conditioning.
3Productivity
If high-resolution ADCs are implemented to support PAM4 modulation standards, then data throughput is improved, but power consumption and cost increase
Solution Approach 1:
The patent segments the high-resolution conversion process into multiple discrete-time phases and uses parallel processing paths with thermometer-to-binary encoding. This segmentation allows the system to achieve high effective resolution for PAM4 modulation support while distributing power consumption across multiple lower-power sub-operations rather than requiring a single high-power converter.
Data Source
AI summary
Methods and systems are provided for circuits. One method is for increasing device threshold voltage distribution of a plurality of devices of a circuit. The method includes adjusting a device threshold voltage of the plurality of devices by different amounts; and selecting a subset of the plurality of devices with adjusted device threshold voltage by a device selection module for performing a function associated with the circuit. In one aspect, a system for device threshold voltage adjustment is provided. The system includes a sensor module for sensing one or more of temperature and voltage values of a die having a plurality of devices for a circuit; and a threshold temperature and voltage compensation module for receiving an input value from the sensor module to compensate variation in a device threshold voltage caused by changes of one or more of temperature and voltage of the die.