Inverter-Based ADC Threshold Tuning for Low-Power High-Speed Conversion
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Solution Overview
Problem
Conventional Analog to Digital Converters (ADCs) face challenges in achieving high dynamic range and low power consumption, particularly in wireless and wireline communication systems, where they consume a significant portion of the total available power and exhibit high conversion latency.
Innovation Solution
The design introduces an inverter-based ADC with a dynamic discrete time architecture, utilizing NMOS and PMOS devices to reduce power consumption by connecting the input signal to the NMOS devices only after an output pre-charge cycle, and employs a multi-bit flash comparator with temperature and voltage compensation to optimize device selection and error correction, thereby enhancing manufacturing yield and reducing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional ADC architectures are used to achieve high conversion rates, then conversion speed is improved, but power consumption increases significantly
Solution Approach 1:
The patent implements a dynamic discrete time architecture where the ADC operates in alternating phases: a pre-charge phase where the output is pre-charged to a reference voltage, and a conversion phase where the actual analog-to-digital conversion occurs. This dynamic switching between operational modes allows the converter to achieve high conversion rates while reducing average power consumption by keeping switching elements inactive during the pre-charge phase.
Solution Approach 2:
The ADC employs periodic operation with distinct time intervals: a pre-charge period followed by a conversion period. During the pre-charge phase, switches are closed to pre-charge the output; during the conversion phase, switches open and the actual conversion occurs. This periodic action pattern enables high throughput while minimizing continuous power dissipation, as the high-current switching paths are activated only periodically rather than continuously.
2Speed
If device scaling is used to improve transition frequency and operation speed, then speed is improved, but analog design parameters such as linearity and dynamic range deteriorate
Solution Approach 1:
The patent replaces traditional analog comparator circuits with a digital inverter-based comparison mechanism. Instead of relying on analog voltage comparisons that are sensitive to device scaling variations, the invention uses digital logic levels and a digital inverter to determine the comparison result. This substitution of analog mechanisms with digital ones allows the system to benefit from scaled device speeds while maintaining robust linearity and dynamic range performance.
3Measurement precision
If conventional ADC designs are used to achieve high dynamic range, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent changes the operational parameters of the ADC by implementing a discrete time architecture with periodic pre-charging. The key parameter change is the temporal separation of pre-charge and conversion operations, allowing the system to achieve high dynamic range during the conversion phase while the average power consumption is reduced through the periodic nature of the operation. The digital inverter-based comparison also changes the power consumption characteristics by using fixed logic levels rather than variable analog currents.
Data Source
AI summary
Methods and devices are provided for circuits. One device includes an adjustment circuit having an adjustable resistor for modifying a resistance value of a resistive device, the adjustment circuit connected to an adjustment terminal of the resistive device. The resistance value of the adjustable resistor changes, when a voltage or charge on the adjustment terminal of the adjustable resistor is changed. The adjustable resistor is a phase change element with an adjusting terminal to which different voltage values are applied for adjusting a conversion device threshold value.