Inverter State Detection Using Shared Binary Sensor Signals

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing converter systems require multiple costly delta-sigma modulators and extensive cabling for analog signal processing, leading to increased manufacturing costs and complexity.

Innovation Solution

A method for determining the state of a converter using a shared clock signal and binary sensor values, which reduces the need for multiple modulators and simplifies cabling by using a shared output line and galvanic separation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If analog galvanic separation is used for each module, then safety is improved, but manufacturing costs increase

Engineering Contradiction:
ImprovesafetyVSAvoidmanufacturing costs
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

Multiple individual analog galvanic separation circuits are merged into a single shared galvanic separation unit. The patent combines the galvanic separation functionality for all modules into one common circuit, eliminating the need for separate delta-sigma modulators in each module while maintaining safety through centralized analog-to-digital conversion and galvanic isolation.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

A single galvanic separation unit serves multiple modules simultaneously. The shared output line and common delta-sigma modulator handle signals from all sensor units, making the galvanic separation system universal rather than module-specific, thereby reducing overall component count and cost.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If individual delta-sigma modulators are used for each module, then signal processing is improved, but device complexity increases

Engineering Contradiction:
Improvesignal processingVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Individual delta-sigma modulators in each module are merged into a single shared modulator. The patent implements one common delta-sigma modulator that processes analog signals from all sensor units through a shared output line, significantly reducing the number of discrete components while maintaining signal processing capability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

A shared output line acts as an intermediary between multiple sensor units and the single delta-sigma modulator. This intermediary transmission path allows multiple analog signals to be conveyed to the common conversion circuit without requiring individual modulators for each sensor unit.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If multiple output lines are used for each module, then signal transmission is improved, but manufacturing effort increases

Engineering Contradiction:
Improvesignal transmissionVSAvoidmanufacturing effort
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

Multiple individual output lines for each module are merged into a single shared output line. The patent implements a common transmission path that carries signals from all sensor units to the shared delta-sigma modulator, eliminating the need for separate cabling for each module and reducing installation complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250183789A1Method for determining the state of an inverter
Publication Date: 2025.06.05 BAUMULLER NURNBERG GMBH
  • US20250183789A1 patent drawing
  • US20250183789A1 patent drawing
  • US20250183789A1 patent drawing

AI summary

A method for determining a state of an inverter on the basis of a plurality of sensor values, each of which corresponds to a measured value created via an analogue sensor of a sensor unit. A clock signal, which has a plurality of identical clock pulses having two different clock states, is sent to each sensor unit. During one of the clock states of each clock pulse, a predefined reference value for each sensor unit is changed by the current measured value to an intermediate value by a predefined operation. During the other clock state of each identical clock pulse, the intermediate value for each sensor unit is changed by an auxiliary value up to the reference value by an opposite operation. During each remaining time span of said identical clock pulse, a first state and otherwise a second state is used as the relevant sensor value.