Inverter Buffer Circuit Topology for Wider Bandwidth and Return Loss

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional inverter buffer circuitries suffer from degraded performance due to low-pass filter effects, which limit 3 dB bandwidth and degrade noise performance and non-linearity, especially when capacitor networks are added to mitigate gate-drain capacitances.

Innovation Solution

The inverter buffer circuitry incorporates coil circuitry connected to an input node and a termination resistor, with a capacitor connected in parallel with the termination resistor and an inductor, effectively canceling out gate-drain capacitances and reducing capacitance loading, thereby improving bandwidth and return loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a capacitor network is added across the virtual ground node to mitigate gate-drain capacitances, then the isolation of ADC dynamics is improved, but the output capacitance increases degrading noise performance and non-linearity

Engineering Contradiction:
Improveisolation of ADC dynamicsVSAvoidnoise performance and non-linearity
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an inductor as an intermediary element between the capacitor network and the virtual ground node. This inductor acts as a mediator that blocks the direct coupling of capacitance to the output while still allowing the capacitor to perform its isolation function. The inductor creates a frequency-dependent impedance that prevents the capacitor's full effect from reaching the output, thus resolving the contradiction between isolation performance and noise/non-linearity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If a termination resistor and feedback resistor are used for unity gain, then the impedance matching is achieved, but a low pass filter is formed degrading the inverter buffer performance

Engineering Contradiction:
Improveimpedance matchingVSAvoidbandwidth
Core Design Contradiction:
Manufacturing precisionVSSpeed

Solution Approach 1:

The patent changes the impedance parameters by introducing inductors in series with the feedback path. This modifies the frequency-dependent impedance characteristics of the feedback network, transforming the low-pass filter behavior into a broadband response. The inductors compensate for the capacitive effects that create the low-pass filtering, thereby extending the bandwidth while maintaining impedance matching through proper selection of L/C ratios.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances 3 dB bandwidth, return loss, and noise performance while maintaining non-linearity, outperforming conventional inverter buffer circuitries by mitigating low-pass filter effects and isolating capacitance loading.

Implementation Method 1

a capacitor connected in parallel with the termination resistor and an inductor, effectively canceling out gate-drain capacitances and reducing capacitance loading

Methodology Applied
Scientific EffectCapacitance cancellation: Capacitance

Implementation Method 2

coil circuitry includes a first inductor and a second inductor... with a capacitor connected in parallel with the termination resistor and an inductor

Methodology Applied
Scientific EffectResonance: Resonance

Data Source

PatentUS12176900B2Buffer circuitry having improved bandwidth and return loss
Publication Date: 2024.12.24 XILINX INC
  • US12176900B2 patent drawing
  • US12176900B2 patent drawing
  • US12176900B2 patent drawing

AI summary

An electronic system includes a buffer and analog-to-digital circuitry. The buffer includes buffer circuitry that includes an input node that receives an input signal. The buffer circuitry further includes coil circuitry that is electrically connected to the input node and a first node. The coil circuitry includes a first inductor and a second inductor. Further, the buffer circuitry includes a resistor that is electrically connected to the first node and a second node. A capacitor of the buffer circuitry is electrically connected to the second node and a third node. The third node is disposed between the first inductor and the second inductor. The buffer circuitry is configured to output an output signal based on the input signal.