Inverter Control Circuit Balancing Switching Element On-State Durations

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Solution Overview

Problem

The existing interconnection inverter systems face issues with unequal on-state durations for positive-side and negative-side switching elements, leading to uneven degradation and shorter lifetimes for negative-side switching elements due to heat generation, as well as complex cooling requirements.

Innovation Solution

A control circuit that generates PWM signals to maintain equal on-state durations for both types of switching elements by using command value signals with specific phase delays and voltage levels, ensuring the waveform of alternating current phase voltage is consistently at predetermined limits for defined periods, thereby balancing the switching activity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If NVS control is performed to reduce switching loss, then switching loss is reduced, but the on-state duration becomes unequal between positive-side and negative-side switching elements

Engineering Contradiction:
Improveswitching lossVSAvoidequality of on-state duration
Core Design Contradiction:
Loss of energyVSStability of the object's composition

Solution Approach 1:

The patent introduces a periodic neutral voltage shift control that shifts the neutral point potential at 1/3-cycle intervals, causing each phase to have a 1/3 cycle where the potential is fixed at negative-side. This periodic action reduces switching frequency and switching loss while maintaining equal on-state durations through coordinated control of all three phases

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent employs asymmetric control by fixing the potential at negative-side during specific 1/3 cycle intervals for each phase, creating deliberate asymmetry in the switching pattern. This asymmetric control strategy, when applied across all three phases with appropriate phase shifts, ultimately achieves symmetric on-state durations for both positive-side and negative-side switching elements

Inventive Principle:
Principle #4Asymmetry

2Loss of energy

If NVS control is performed to reduce switching loss, then switching loss is reduced, but cooling requirements become complex

Engineering Contradiction:
Improveswitching lossVSAvoidcooling system complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

By implementing periodic neutral voltage shift control that fixes potential at negative-side for 1/3 cycle intervals, the patent reduces the frequency and intensity of heat generation in switching elements. This periodic operation allows for more uniform heat distribution and reduces the complexity of cooling system design

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent creates equipotential conditions by fixing the neutral point potential at the negative-side potential during specific intervals. This equipotential control reduces voltage stress and heat generation asymmetry, simplifying the thermal management requirements for switching elements

Inventive Principle:
Principle #12Equipotentiality

Data Source

PatentUS10389269B2Inverter apparatus including control circuit employing two-phase modulation control, and interconnection inverter system including the inverter apparatus
Publication Date: 2019.08.20 DAIHEN CORP
  • US10389269B2 patent drawing
  • US10389269B2 patent drawing
  • US10389269B2 patent drawing

AI summary

A control circuit reduces switching loss by periodically stopping switching elements, and reduces the difference between the time for which positive switching elements are in on state and the time for which negative switching elements are in on state. The control circuit includes a command value signal generator generating command value signals Xu1, Xv1, and Xw1 from line voltage command value signals Xuv, Xvw, and Xwu, and includes a PWM signal generator generating PWM signals by the command value signals Xu1, Xv1, and Xw1. The command value signals Xu1, Xv1, and Xw1 are continuously at “0” for a predetermined period, and are continuously at “2” for another period. This enables reducing the difference between the period for which the PWM signals are low and the period for which they are highl.