Inverter-Based CTLE Topology for Low-Power Linear Equalization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Inverter-based continuous time linear equalizers (CTLEs) face challenges in achieving low power consumption and linearity, with aggressive equalization requiring higher power and common mode mismatch leading to nonlinearity issues.
Innovation Solution
The design incorporates a configuration of inverters, capacitors, and resistors to form specific topologies such as additive and subtractive structures, with a capacitor coupled between the inputs of two inverters and a resistor between a common-mode voltage and one inverter, optimizing power consumption and linearity by adjusting the transconductance and capacitance of the inverters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If inverter-based CTLE topology is used to reduce die area, then area is reduced, but power consumption and linearity become dependent on topology and inverter sizing making optimization difficult
Solution Approach 1:
The CTLE is segmented into multiple inverter stages (first inverter, second inverter, third inverter) with distinct functions. Each inverter is sized and biased independently to optimize overall performance. The capacitor and resistor are segmented to provide specific frequency-dependent functionality without requiring complex topologies.
Solution Approach 2:
Different inverters are assigned different transconductance values (gm1, gm2, gmL) to create local variations in gain characteristics. The first and second inverters have different transconductances to achieve differential signaling with optimized linearity, while the third inverter provides buffered output with appropriate drive strength.
2Reliability
If aggressive equalization is implemented to improve signal quality, then performance is improved, but power consumption increases
Solution Approach 1:
The equalization strength is made dynamic through frequency-dependent filtering. The capacitor coupled between the first and second inverters creates a high-pass filter that provides aggressive equalization at high frequencies where it is most needed, while allowing low frequencies to pass with minimal processing, thereby reducing overall power consumption.
Solution Approach 2:
The transconductance parameters of the inverters are carefully selected to achieve the desired equalization profile. By optimizing gm1, gm2, and gmL, the circuit achieves strong equalization performance without requiring excessive bias currents, thus controlling power consumption while maintaining signal quality.
3Ease of operation
If common mode voltage is used to bias inverters, then circuit operation is enabled, but common mode mismatch causes linearity problems
Solution Approach 1:
The circuit intentionally uses asymmetric inverter sizing and transconductance values to achieve symmetric differential operation. The first and second inverters have different transconductances (gm1 and gm2) but are configured to produce matched differential outputs, canceling common mode errors and improving linearity.
Solution Approach 2:
The capacitor coupled between the first and second inverters acts as an intermediary that couples their outputs differentially while blocking common mode signals. This intermediary element helps maintain linearity by preventing common mode mismatch from propagating to the output.
Data Source
AI summary
An example continuous time linear equalizer (CTLE) includes a first inverter; a second inverter having an input to receive an input signal; a capacitor coupled between an input of the first inverter and the input of the second inverter; a resistor coupled between a common-mode voltage and the input of the first inverter; a third inverter having an output to provide an output signal; and a node comprising an output of the first inverter, an output of the second inverter, an input of the third inverter, and the output of the third inverter.