Inverter Delay Chain for Data-Clock Skew Correction
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Solution Overview
Problem
In source synchronous systems, skew between data signals and clock signals can lead to incorrect identification of data pulse levels, especially as frequency increases, due to deviations in clock transitions from optimal times.
Innovation Solution
A memory system with a delay circuit and skew correction circuit that adjusts the number of inverters to correct skew by delaying data signals and inverting them if necessary, ensuring accurate alignment with clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of data and clock signals is increased to improve productivity, then the data transmission speed is improved, but the skew between data signals and clock signals is magnified causing incorrect data identification
Solution Approach 1:
The patent implements dynamic skew correction by making the delay circuit adjustable based on operating conditions. The system dynamically selects different delay amounts (first, second, or third delay) depending on the data signal frequency and skew conditions, allowing the receiver to adapt to varying skew magnitudes at different frequencies. This dynamic adjustment resolves the contradiction by maintaining reliable data identification across a wide frequency range.
Solution Approach 2:
The patent changes the delay parameter of the data signal to correct skew. By adjusting the delay amount (changing the time parameter) based on measured skew conditions, the system compensates for frequency-dependent skew effects. The receiver can select from multiple delay configurations to optimize the alignment between data and clock signals at different operating frequencies.
2Reliability
If delay circuits are added to correct skew between data and clock signals, then data identification accuracy is improved, but device complexity increases
Solution Approach 1:
The delay correction function is segmented into discrete, selectable delay stages (first delay circuit, second delay circuit, third delay circuit). Each stage provides a specific delay amount, and the system selects the appropriate segment based on the skew condition. This segmentation allows for manageable complexity while providing effective skew correction across different frequency ranges.
Solution Approach 2:
The system performs self-adjustment by measuring the skew between data and clock signals and automatically selecting the appropriate delay configuration. The receiver monitors data identification accuracy and adjusts the delay circuit selection accordingly, eliminating the need for external calibration or complex control mechanisms. This self-service approach maintains reliability while minimizing added complexity.
Data Source
AI summary
Technology is disclosed herein for correcting skew between data signals and a clock signal. In one aspect, a memory system has a delay circuit having delay blocks, with each delay block having one or more inverters. The delay circuit is configured to pass a data signal through either an odd number of the inverters or an even number of the inverters to produce a delayed data signal. The memory system has a skew correction circuit configured to control the number of inverters in the delay circuit through which the data signal is passed in order to correct skew between the data signal and the clock signal. The memory system has a polarity correction circuit configured to invert the data signal in the event that the delay circuit passed the data signal through the odd number of the inverters.