Inverter Delay Element with Adjustable Current for Stable Timing

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Solution Overview

Problem

Integrated circuit delay elements are sensitive to process and supply voltage variations, leading to inconsistent performance across different regions of the IC.

Innovation Solution

An inverter-based delay element with adjustable current source/sink is implemented, where the size of the current source and sink are controlled based on process speed and supply voltage to minimize delay sensitivity. This is achieved through a configuration of field effect transistors and control voltages that adjust the delay between input and output signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If delay elements are used in integrated circuits, then signal timing operations can be performed, but the delay performance becomes sensitive to process and supply voltage variations

Engineering Contradiction:
Improvedelay consistencyVSAvoidprocess and supply voltage variation sensitivity
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the electrical parameters (current source/sink strengths) of the delay element based on detected process speed and supply voltage conditions. By dynamically adjusting these parameters, the delay element compensates for process and voltage variations, maintaining consistent delay performance across different operating conditions and IC regions.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements a feedback mechanism where the actual delay performance is monitored and used to adjust the current source/sink parameters. This closed-loop control allows the system to automatically compensate for process and voltage variations, ensuring reliable and consistent delay operation despite environmental changes.

Inventive Principle:
Principle #23Feedback

2Reliability

If the size of current source and sink are adjusted to reduce delay sensitivity, then delay consistency improves, but device complexity increases

Engineering Contradiction:
Improvedelay consistencyVSAvoidcontrol circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the control function into distinct components: process speed detection, supply voltage detection, and current source/sink adjustment. Each function is handled by separate circuit blocks that work together, making the overall complex system manageable and implementable using standard IC design practices.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces the sensitivity of delay elements to process and supply voltage variations, ensuring consistent performance across different regions of the integrated circuit.

Implementation Method 1

a first set of field effect transistors (FETs) including a first set of gates coupled together and configured to receive a first control voltage; a second set of FETs coupled in series with the first set of FETs between a first voltage rail and a first node

Methodology Applied
Scientific EffectField effect transistor operation:

Data Source

PatentUS11489518B2Inverter-based delay element with adjustable current source/sink to reduce delay sensitivity to process and supply voltage variation
Publication Date: 2022.11.01 QUALCOMM INC
  • US11489518B2 patent drawing
  • US11489518B2 patent drawing
  • US11489518B2 patent drawing

AI summary

A delay element including a first set of field effect transistors (FETs) with gates configured to receive a first control voltage; a second set of FETs coupled in series with the first set of FETs between a first voltage rail and a first node, respectively, the second set of FETs include gates configured to receive a set of complementary select signals, respectively; a third set of FETs including gates configured to receive a set of non-complementary select signals, respectively; a fourth set of FETs coupled in series with the third set of FETs between a second node and a second voltage rail, respectively, the fourth set of FETs including gates configured to receive a second control voltage; and an inverter coupled between the first node and the second node, the inverter including an input configured to receive an input signal and an output configured to produce an output signal.