Inverter Clock Frequency Dithering for EMI Reduction
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Solution Overview
Problem
Electronic devices with inverters often generate excessive electromagnetic interference (EMI) due to the operation of these devices, which can be problematic for converting direct current (DC) to alternating current (AC) power using a single clock signal frequency.
Innovation Solution
The implementation of a dithered clock signal with multiple frequency levels, controlled by a modulating signal, is used to reduce EMI by spreading the frequency spectrum of the alternating current signals output by the inverter, thereby minimizing electromagnetic emission at specific frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a single clock signal frequency is used in the inverter, then the inverter operation is simple and stable, but electromagnetic interference (EMI) increases
Solution Approach 1:
The patent applies dynamics by transitioning from a static single-frequency clock signal to a dynamic multi-frequency clock signal. The inverter switches between multiple clock frequencies (first frequency, second frequency, third frequency) based on operational requirements, making the system adaptive and dynamic rather than fixed, thereby reducing EMI through frequency variation.
Solution Approach 2:
The patent implements parameter changes by varying the clock signal frequency parameter. Instead of using a constant frequency, the system changes the frequency parameter to three different values (first frequency lower than fundamental, fundamental frequency, and second frequency higher than fundamental), which spreads the electromagnetic spectrum and reduces peak EMI emissions.
2Object-affected harmful factors
If multiple frequency levels are used in the clock signal, then electromagnetic interference is reduced, but the control circuitry complexity increases
Solution Approach 1:
The patent applies periodic action by using a modulating signal with a repeated cycle to control the switching between different clock frequencies. The modulating signal periodically transitions the clock signal through the three frequency levels in a systematic pattern, providing structured and predictable control that manages complexity through regularity.
Solution Approach 2:
The patent introduces an intermediary modulating signal that mediates between the control circuitry and the clock signal generation. This modulating signal serves as an intermediate control layer that simplifies the overall control architecture by providing a standardized interface for frequency switching, thereby managing control circuitry complexity.
3Object-affected harmful factors
If the clock signal spends fewer periods at the fundamental frequency, then electromagnetic emission at specific frequencies is minimized, but the power conversion efficiency may be affected
Solution Approach 1:
The patent applies parameter changes by adjusting the duty cycle distribution across different frequency levels. The clock signal is configured to spend fewer periods at the fundamental frequency and more periods at the first and second frequencies, changing the operational parameters to spread electromagnetic emissions while maintaining acceptable power conversion efficiency through optimized frequency distribution.
Solution Approach 2:
The patent applies local quality by differentiating the time spent at each frequency level rather than uniform distribution. Specifically, the fundamental frequency is assigned fewer periods compared to the first and second frequencies, creating a non-uniform local characteristic in the frequency spectrum that reduces peak emissions while maintaining overall system performance.
Data Source
AI summary
An electronic device may include an inverter. The inverter may convert direct current (DC) power to alternating current (AC) power. The inverter may use a clock signal at a given frequency to output corresponding alternating current signals at the given frequency. The inverter may receive a dithered clock signal that is frequency dithered using a modulating signal. The dithered clock signal may have at least three different frequency levels during a repeated cycle of the modulating signal. The at least three different frequency levels may include a fundamental frequency, a first frequency that is lower than the fundamental frequency, and a second frequency that is higher than the fundamental frequency. The dithered clock signal may be, during the repeated cycle of the modulating signal, at the fundamental frequency for fewer total periods than at the first frequency and for fewer total periods than at the second frequency.