Inverter Gate Drive Synchronization via Embedded Clock Signals
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Solution Overview
Problem
Large motor drives using parallel inverter topologies face challenges in maintaining synchronous operation due to mismatched switching timing, leading to circulating currents, and existing techniques lack efficient methods for precise switching and synchronization.
Innovation Solution
A system with control circuitry generating timing signals to synchronize the operational state changes of multiple parallel inverters, using fiber optic cables to convey embedded data and clock information, and power layer circuitry to compute and apply these signals to solid state switches, ensuring synchronized switching and reducing circulating currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple inverters are operated in parallel to handle large motor drives, then the power handling capability is improved, but synchronization precision deteriorates due to mismatched switching timing
Solution Approach 1:
The control circuitry generates timing signals in advance that embed both data and clock information, which are then transmitted to each inverter's power layer circuitry. This preliminary action ensures that all inverters are pre-synchronized before switching operations begin, eliminating timing mismatches that would otherwise occur during parallel operation.
Solution Approach 2:
The system transmits timing signals containing embedded clock information from a central control circuitry to each inverter, and the power layer circuitry computes timing based on this feedback. This closed-loop feedback mechanism ensures that even with variations in signal transmission, each inverter can adjust its switching timing to maintain precise synchronization across all parallel inverters.
2Reliability
If magnetic structures are added to prevent circulating currents, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent replaces magnetic structures with an electronic control system that generates precise timing signals embedded with clock information. Instead of using physical magnetic components to prevent circulating currents, the system uses synchronized gate drive signals controlled by a central microprocessor, substituting mechanical/magnetic solutions with electronic control.
Solution Approach 2:
The control circuitry acts as an intermediary that generates and distributes synchronized timing signals to all parallel inverters. This intermediary system coordinates the switching operations of all inverters, preventing circulating currents through precise timing control rather than through magnetic isolation structures.
3Productivity
If switching frequency is increased to improve power conversion efficiency, then the productivity is improved, but the difficulty of detecting and measuring timing synchronization increases
Solution Approach 1:
The timing signals serve as an intermediary that carries embedded clock information from the control circuitry to each inverter. This intermediary signal provides a reference that makes high-frequency switching synchronization measurable and controllable, allowing the system to achieve high productivity while maintaining detectable timing relationships.
Solution Approach 2:
The system preliminarily establishes timing synchronization by embedding clock information in control signals before the high-frequency switching occurs. This preliminary timing establishment makes it easier to detect and measure synchronization even at high switching frequencies, as the reference timing is already embedded in the control signals.
Data Source
AI summary
Techniques include systems and methods of synchronizing multiple parallel inverters in a power converter system. In one embodiment, control circuitry is connected to a power layer interface circuitry at each of the parallel inverters, via an optical fiber interface. The system is synchronized by transmitting a synchronizing pulse to each of the inverters. Depending on the operational mode of the system, different data exchanges may occur in response to the pulse. In an off mode, power up and power down data may be exchanged between the control circuitry and the inverters. In an initiating mode, identification data may be transmitted from the inverters to the control circuitry. In an active mode, control data may be sent from the control circuitry to the inverters. In some embodiments, the inverters also transmit feedback data and/or acknowledgement signals to the control circuitry. Power layer circuitry of the inverter adjusts a local clock based upon sampled data from the control circuitry to maintain synchronicity of the inverters between synchronization pulses.