Inverter Gate Resistance Control for High Voltage Start-up
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Solution Overview
Problem
Solar power inverter systems face challenges in accommodating high DC source voltages during start-up, particularly when the open-circuit voltage of a PV array approaches the blocking voltage rating of semiconductor devices, leading to voltage overshoot issues that can exceed the safe operating limits of the inverter system.
Innovation Solution
A power inverter system with a controller that increases the gate turn-off resistance of semiconductor switching devices during start-up periods, coupled with a DC link capacitor, to prevent the DC link voltage from exceeding the blocking voltage rating, and reduces gate resistance when the PV array voltage reaches a safe operating condition, thereby avoiding voltage overshoot and maintaining efficient operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the inverter system is designed to accommodate high open-circuit voltage from PV arrays, then the system can handle higher voltage sources, but the DC link voltage may exceed the blocking voltage rating of semiconductor devices during start-up due to voltage overshoot
Solution Approach 1:
The controller detects start-up conditions and proactively increases the gate turn-off resistance before voltage overshoot can occur. This preliminary action prevents the harmful voltage spike from exceeding semiconductor blocking voltage ratings, allowing the system to safely accommodate high open-circuit voltage sources.
Solution Approach 2:
The gate turn-off resistance is dynamically changed based on operating conditions. During start-up, the resistance is increased to limit voltage overshoot, while during normal operation, the resistance returns to its standard value for optimal switching performance. This parameter change resolves the contradiction between handling high voltages and protecting devices.
2Reliability
If the gate turn-off resistance is increased during start-up to prevent voltage overshoot, then semiconductor devices are protected from overvoltage, but switching losses increase and switching speed decreases
Solution Approach 1:
The increased gate resistance is applied only periodically during the start-up phase when high voltage protection is needed, rather than continuously. Once the system reaches normal operating conditions, the resistance returns to its standard low value, minimizing switching losses during the majority of operation time while still providing protection when needed.
Solution Approach 2:
The high resistance is applied only during the brief start-up period before normal operation begins. This preliminary protective action lasts only as long as necessary to bring the system to a safe operating state, thereby limiting energy losses to a minimal time window while ensuring device protection during the critical transition phase.
3Productivity
If the gate resistance remains low for fast switching, then switching speed is high and efficiency is improved, but voltage overshoot occurs during start-up that can exceed blocking voltage ratings
Solution Approach 1:
The gate resistance is made dynamic rather than fixed, changing its value based on the operating state of the inverter. During start-up, the resistance increases to suppress voltage overshoot, while during normal operation, it decreases to enable fast switching. This dynamic adaptation resolves the contradiction between switching speed and voltage control.
Solution Approach 2:
The high resistance characteristic is applied locally in time and space - specifically during the start-up period and only for the gate turn-off path. The rest of the system operates with standard low resistance for optimal performance. This localized application of high resistance eliminates voltage overshoot during the critical start-up phase without affecting overall system efficiency.
Data Source
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AI summary
A power inverter system (10) includes a plurality of power semiconductor switching devices (38). Each switching device (38) includes a corresponding gate turn off resistance (40) configured to increase during starting up periods of the inverter system (10) such that the open circuit voltage of a corresponding power source (12) providing power to the power inverter system (10) does not exceed the switching device (38) blocking voltage ratings during the corresponding switching turn-off periods. The starting up period is the time required to bring the corresponding power source (12) voltage from its open circuit voltage level to a predetermined voltage which constitutes a safe operating condition for the plurality of power semiconductor switching devices (38).