Inverter-Based Glitch Detection for Low-Area Power Attack Sensing
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Solution Overview
Problem
Conventional glitch detectors for detecting power attacks on chips have high power consumption or require large chip areas, making them unsuitable for integration into chips.
Innovation Solution
A glitch detector design utilizing inverters, charge sharing components, and warning flag generators to detect under and over voltage glitches without passive elements, reducing chip area and enabling effective detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a comparator-based glitch detector is used, then detection capability is provided, but power consumption increases
Solution Approach 1:
The patent extracts and removes the comparator component from the glitch detector, replacing it with an inverter-based circuit. This extraction of the high-power comparator element directly reduces power consumption while maintaining glitch detection functionality through the inverter's voltage threshold response characteristics.
Solution Approach 2:
The patent employs simple inverter circuits instead of complex comparators, using basic, low-power components that can be easily replaced or reset. The inverter-based design uses inexpensive, low-power elements that consume minimal energy during operation.
2Reliability
If an RC-trigger type detector is used, then glitch detection is enabled, but chip area increases due to passive devices
Solution Approach 1:
The patent removes passive RC (resistor-capacitor) trigger components from the detector design. By extracting these area-consuming passive devices and replacing them with active inverter-based logic, the chip area is significantly reduced while glitch detection remains functional through the inverter's voltage response.
Solution Approach 2:
The patent substitutes passive electrical components (RC circuits) with active semiconductor logic elements (inverters). This substitution replaces the mechanical/passive system with an active electronic system that achieves the same detection function using fewer physical components and less chip area.
3Reliability
If conventional glitch detectors are used, then power attacks can be detected, but device complexity and chip area increase
Solution Approach 1:
The patent extracts and removes complex detector structures and passive components, simplifying the overall device architecture. By taking out unnecessary elements and retaining only the essential inverter-based voltage response mechanism, the device complexity is reduced while maintaining power attack detection capability.
Solution Approach 2:
Instead of using complex detectors to simplify the system, the patent inverts the approach by using simple inverter circuits to perform the detection function. This inversion from complex-to-simple design philosophy reduces device complexity while achieving the same security objective.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed glitch detector effectively detects under and over voltage glitches with minimal chip area requirements, facilitating integration into processors.
Implementation Method 1
The first inverter is configured to receive a first signal at a first node to generate a second signal to a second node
Implementation Method 2
The second inverter is configured to receive the second signal at the second node to generate the first signal to the first node
Implementation Method 3
The charge sharing component is coupled between the first node and the second node, and is configured to selectively connect the first node to the second node
Implementation Method 4
The bleeding path is configured to selectively provide a current path between the second node and a reference voltage
Implementation Method 5
The warning flag generator is coupled to the first node or the second node, and configured to determine whether a supply voltage of the glitch detector suffers an under voltage glitch according to a voltage level of the first signal or a voltage level of the second signal
Data Source
AI summary
The present invention provides a glitch detector including a first inverter, second inverter, a charge sharing component and a warning flag generator. The first inverter is configured to receive a first signal at a first node to generate a second signal to a second node. The second inverter is configured to receive the second signal at the second node to generate the first signal to the first node. The charge sharing component is configured to selectively connect the first node to the second node. The warning flag generator is coupled to the first node or the second node, and configured to determine whether a supply voltage of the glitch detector suffers an under voltage glitch according to a voltage level of the first signal or a voltage level of the second signal, to determine whether to output a warning flag.