Inverter Level Skip Prevention Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing inverter systems face challenges in preventing line-to-line voltage level skipping, particularly in systems with an arbitrary number of phases and levels, due to limitations in modulation techniques and hardware constraints, which can lead to dielectric breakdown and increased device size when using output filters for surge suppression.
Innovation Solution
An inverter system with a level skip prevention control section that employs counters to inhibit upward and downward shifts of output voltage levels, delaying these shifts by a control interval to prevent line-to-line voltage level skipping, and uses a gate signal generation section to manage the output voltage levels based on voltage level commands and previous output levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If output filters are added for surge suppression, then dielectric breakdown is prevented, but device size increases
Solution Approach 1:
The patent replaces the mechanical/electrical output filter system with a control-based solution. The level skip prevention control section uses software/firmware logic to detect and prevent voltage level skipping by adjusting switching timing, eliminating the need for physical surge suppression filters while maintaining dielectric protection.
Solution Approach 2:
The control system performs preliminary detection of voltage level changes and proactively adjusts switching timing before dangerous voltage stress occurs. By monitoring phase voltage levels and predicting potential line-to-line voltage skipping, the system prevents dielectric breakdown before it happens, rather than requiring filters to suppress surges after they occur.
2Reliability
If carrier frequency is increased to prevent level skipping, then line-to-line voltage level skipping is suppressed, but switching loss increases
Solution Approach 1:
Instead of uniformly increasing carrier frequency across all operating conditions, the patent applies partial action by only adjusting switching timing when level skipping is detected. The control system monitors voltage levels and selectively modifies switching patterns only when necessary, maintaining normal carrier frequency and low switching loss during normal operation while preventing level skipping when needed.
Solution Approach 2:
The patent implements dynamic switching timing adjustment based on real-time voltage level monitoring. The carrier frequency and switching timing are made variable rather than fixed, allowing the system to adapt switching patterns dynamically to prevent level skipping only when voltage conditions require it, thereby minimizing overall switching loss while maintaining reliability.
3Reliability
If switching timing is delayed to prevent two-step shift, then line-to-line voltage level skipping is prevented, but voltage updating delay increases
Solution Approach 1:
The patent applies local quality by selectively delaying switching timing only for specific phases and specific switching events where level skipping is detected, rather than uniformly delaying all switching operations. The control system identifies which phase transitions cause level skipping and applies timing adjustment only to those specific cases, maintaining fast voltage updating for other operations.
Solution Approach 2:
The patent introduces an intermediary control layer (level skip prevention control section) that sits between the voltage level command and the actual switching execution. This intermediary monitors voltage levels and intelligently adjusts timing only when necessary, acting as a mediator that prevents level skipping without causing systematic delays in CPU voltage updating for all operations.
Data Source
AI summary
An inverter system includes a level skip prevention control section. The level skip prevention control section is configured to: in response to an upward shift of an output voltage level of a first one of phases, set a counter for inhibiting upward shifting of the output voltage level of the first phase during a predetermined duration, and set a counter for inhibiting downward shifting of an output voltage level of a second one of the phases other than the first phase during a predetermined duration; and in response to a downward shift of the output voltage level of the first phase, set a counter for inhibiting downward shifting of the output voltage level of the first phase during a predetermined duration, and set a counter for inhibiting upward shifting of the output voltage level of the second phase during a predetermined duration.


