Inverter Loop Merging Latch and Sense Amplifier Functions
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Solution Overview
Problem
Conventional data holding devices face challenges in reducing circuit scale, utilizing inverter loops for both latch and sensing functions, and ensuring reliable data protection and reading margin due to variations in ferroelectric element effective areas.
Innovation Solution
A data holding device with an inverter loop comprising two inverters connected in a loop, a differential pair circuit, and potential setters to control node potentials, along with a nonvolatile storing portion using hysteresis characteristics of ferroelectric elements and a sense amplifier to improve data reading accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate inverter loops are used for latch and sense amplifier functions, then each function can be independently optimized, but circuit scale increases
Solution Approach 1:
The patent merges the latch function and sense amplifier function into a single inverter loop structure. The sense amplifier utilizes the same inverter loop that serves as the latch, eliminating the need for separate inverter loops while maintaining both functions. This is achieved by configuring the sense amplifier to operate on the output nodes of the latch inverter loop, thereby reducing circuit area without sacrificing functional independence.
Solution Approach 2:
The inverter loop is designed to serve multiple functions: it acts as both the latch for data holding and the sense amplifier for data sensing. By making the inverter loop universal, the patent eliminates redundant circuitry while ensuring that both latch and sense amplifier operations can be performed reliably within the same structural framework.
2Measurement precision
If inverter loop is dedicated only for sensing function, then sensing performance is optimized, but latch function requires additional circuitry
Solution Approach 1:
The inverter loop is configured to perform both sensing and latch functions simultaneously. The sense amplifier operation leverages the inverter loop's inherent amplification capability, while the latch function utilizes the same inverter loop's state-holding capability. This multi-functional design eliminates the need for separate dedicated circuits for each function.
3Ease of manufacture
If ferroelectric elements with different effective areas are used, then manufacturing flexibility increases, but offset fluctuation occurs reducing operation margin
Solution Approach 1:
The patent introduces a feedback mechanism where the sense amplifier reads the data from the ferroelectric elements and feeds it back to the latch. This feedback loop allows the system to compensate for offset fluctuations caused by variations in ferroelectric element effective areas. The sense amplifier detects the actual state including any offsets, and the feedback ensures accurate data holding despite manufacturing variations.
Solution Approach 2:
The patent utilizes the hysteresis characteristics of ferroelectric elements, which provide a stable switching behavior that is relatively insensitive to variations in effective area. By operating in the hysteresis region and utilizing the remanent polarization states, the system maintains reliable operation margins even when ferroelectric element parameters vary due to manufacturing tolerances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables both latch and sensing functions using a single inverter loop, reduces circuit area, and enhances data protection and reading margin by controlling node potentials and utilizing hysteresis characteristics of ferroelectric elements.
Implementation Method 1
a nonvolatile storing portion (NVM) that stores the data signal D in a nonvolatile manner by using hysteresis characteristics of the ferroelectric elements
Implementation Method 2
input signals SDnC and SDC corresponding to the complementary data described above are generated using capacitive coupling between the ferroelectric elements CL1a and CL1b, and capacitive coupling between the ferroelectric elements CL2a and CL2b, and a logic level of the data signal D is determined based on a magnitude relationship between them
Data Source
AI summary
A data holding device 100 has an inverter loop 101, a differential pair circuit 102 connected to the ground terminals of inverters, a first potential setter 103 configured to turn the output terminals of the inverters to a first potential (VDD), and a second potential setter 104 configured to turn the ground terminals of the inverters to a second potential (VSS). During data holding, the differential pair circuit 102 and the first potential setter 103 are disabled so that the ground terminals of the inverters are at the second potential. During data writing, the differential pair circuit 102 is disabled so that the output terminal of one inverter is at the first potential and the ground terminal of the other inverter is at the second potential.