Asymmetric Inverter Noise Filter With Latch-Based Dead Time
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Solution Overview
Problem
Designing electronic circuits with a simple structure that effectively remove noise and manage dead time is challenging due to the complexity of existing noise filter, dead time, and delay circuits.
Innovation Solution
A noise filter circuit and dead time circuit are designed using a combination of inverter circuits with conductivity-type transistors of varying capabilities, where one transistor has a lower capability than the other, and a latch circuit to process signals, allowing for efficient noise removal and dead time management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional noise filter circuits are used, then noise removal capability is achieved, but circuit structure becomes complex and chip size increases
Solution Approach 1:
The patent combines multiple functions (noise filtering, dead time generation, signal delay) into a single integrated circuit block. The inverter circuits with asymmetric transistor capabilities serve dual purposes: they filter noise while simultaneously generating dead time and delaying signals, eliminating the need for separate circuits for each function.
Solution Approach 2:
The inverter circuit with asymmetric transistors is designed as a universal building block that performs multiple functions. By adjusting the capability difference between transistors, the same circuit structure can provide noise filtering, dead time generation, and variable signal delay, making it adaptable to different operational requirements without changing the basic architecture.
2Reliability
If conventional dead time circuits are used, then dead time management is achieved, but circuit structure becomes complex and chip size increases
Solution Approach 1:
The patent integrates dead time generation functionality within the inverter circuit structure. The asymmetric transistor capabilities naturally create a time delay between the input signal and output signal transitions, providing dead time without requiring separate timing circuits or additional components.
3Loss of time
If conventional delay circuits are used, then signal delay is achieved, but circuit structure becomes complex and chip size increases
Solution Approach 1:
The patent combines signal delay functionality with noise filtering and dead time generation in a single inverter circuit. The inherent asymmetry in transistor capabilities creates a natural delay effect that is integrated into the signal processing path, eliminating the need for separate delay circuits.
4Device complexity
If circuit structure is simplified, then chip size is reduced, but noise filtering and dead time management capabilities are compromised
Solution Approach 1:
The patent achieves noise filtering capability by controlling the electrical parameters (capability) of the transistors rather than adding more circuit stages. By carefully selecting the capability ratio between asymmetric transistors, the circuit provides effective noise filtering while maintaining a simple two-transistor inverter structure.
Data Source
AI summary
A noise filter circuit includes a first inverter circuit that receives a signal based on an input signal, a second inverter circuit that receives a signal based on the input signal, and a latch circuit that receives signals based on a signal output from the first inverter circuit and a signal based on a signal output from the second inverter circuit as a set signal and a reset signal. Each of the first inverter circuit and the second inverter circuit includes a first-conductivity-type transistor and a second-conductivity-type transistor, the capability of one of the first-conductivity-type transistor and the second-conductivity-type transistor being lower than the capability of the other of the first-conductivity-type transistor and the second-conductivity-type transistor.