Multilevel Inverter Offset Voltage Control for Failed Cell Redundancy

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Solution Overview

Problem

Cascaded H-bridge (CHB) multilevel inverters face challenges in maintaining three-phase line-to-line output voltage equivalence when power cells fail, leading to reduced redundancy and output voltage, due to the need to bypass failed cells.

Innovation Solution

A method is introduced to calculate an offset voltage (or zero sequence voltage) using phase voltage references and a limiter, which is injected to maintain three-phase equivalent voltage control without bypassing operational power cells, ensuring continuity and maximum line-to-line voltage output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If power cells are bypassed when they fail in a CHB multilevel inverter, then continuous operation is enabled, but three-phase line-to-line voltage equivalence is lost and output voltage is reduced

Engineering Contradiction:
Improvecontinuous operationVSAvoidthree-phase line-to-line voltage equivalence
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the voltage reference parameters by calculating an offset voltage based on the sum of DC link voltages of normally operating power cells. This offset voltage is added to the original voltage reference to generate a new voltage reference that compensates for the bypassed cells, thereby maintaining three-phase voltage equivalence while enabling continuous operation with reduced redundancy.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If power cells are bypassed to maintain operation, then system continuity is achieved, but redundancy is decreased

Engineering Contradiction:
Improveoperation continuityVSAvoidredundancy
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent dynamically adjusts the voltage reference parameters based on the operational status of power cells. By calculating the offset voltage from the sum of DC link voltages of functioning cells and adding it to the voltage reference, the system maintains full voltage output capability even when some power cells are bypassed, thereby preserving redundancy while ensuring continuous operation.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If offset voltage is injected to maintain voltage equivalence, then three-phase line-to-line voltage equivalence is maintained, but control complexity increases

Engineering Contradiction:
Improvethree-phase line-to-line voltage equivalenceVSAvoidcontrol complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent replaces complex mechanical or hardware-based voltage balancing mechanisms with a computational approach. By using mathematical calculations to determine the offset voltage based on DC link voltages and injecting this calculated offset into the voltage reference, the system achieves precise three-phase voltage equivalence control through software/algorithms rather than complex hardware circuits.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentEP3220529B1Method for controlling three phase equivalent voltage of multilevel inverter
Publication Date: 2020.09.23 LSIS CO LTD
  • EP3220529B1 patent drawingFigure 1
  • EP3220529B1 patent drawingFigure 2
  • EP3220529B1 patent drawingFigure 3

AI summary

Provided is a method of controlling a three phase equivalent voltage in a multilevel inverter including sensing a state of each of power cells (120) of the multilevel inverter to determine whether or not failure occurs at each of the power cells, bypassing power cells which are determined as being failed to connect power cells operating normally to each other in series per each phase, calculating an offset voltage value using a phase voltage reference per each phase and a sum of each of direct current, DC, link voltages of the power cells which operate normally and configure each of the phases, and calculating a pole voltage reference per each phase for maintaining an equivalence of a three phase line-to-line output voltage using the phase voltage reference per each phase and the calculated offset voltage.