Inverter PWM Buffer Fault Detection via Feedback Unit
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Solution Overview
Problem
Conventional inverter control systems may output abnormal PWM signals when a fault occurs in the buffer unit, potentially leading to incorrect motor control and safety issues.
Innovation Solution
The inverter control device incorporates a feedback unit that feeds back the PWM signal to the arithmetic unit, allowing it to output a redundant or protection operation PWM signal via a second buffer unit with a lower fault rate, preventing erroneous signals from reaching the drive unit and ensuring safe operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a buffer unit is used to output PWM signals from the arithmetic unit, then the signal transmission function is achieved, but the reliability deteriorates when a fault occurs in the buffer unit causing abnormal PWM signals to be outputted
Solution Approach 1:
The patent implements a feedback unit that receives the PWM signal from the buffer unit and feeds it back to the arithmetic unit. This feedback mechanism enables the arithmetic unit to detect faults in the buffer unit by monitoring the PWM signal integrity, allowing the system to identify when abnormal signals are being outputted and take corrective action.
Solution Approach 2:
The feedback unit acts as an intermediary between the buffer unit and the arithmetic unit. It monitors the PWM signal transmitted through the buffer unit and provides fault information back to the arithmetic unit, enabling indirect detection of buffer unit faults without directly interfering with the primary signal transmission path.
2Reliability
If fault detection is implemented by feeding back the PWM signal to the arithmetic unit, then the fault detection capability is improved, but the device complexity increases due to the additional feedback unit
Solution Approach 1:
The feedback unit serves multiple functions: it transmits the PWM signal from the buffer unit back to the arithmetic unit for fault detection, and also provides a communication path for the arithmetic unit to send control signals to the buffer unit. This multi-functionality reduces the need for separate dedicated fault detection circuitry.
Solution Approach 2:
The arithmetic unit performs fault detection using its existing processing capabilities by receiving and analyzing the feedback PWM signal. Rather than requiring a separate dedicated fault detection device, the arithmetic unit leverages its own computational resources to monitor system health, reducing overall device complexity.
Data Source
AI summary
If a fault occurs in a buffer unit from which a PWM signal is outputted, an abnormal PWM signal may be outputted from the buffer unit. When a fault occurs in a first buffer unit, a fault detection unit detects a fault in the PWM signal being inputted via a second buffer unit. When the fault in the PWM signal is detected, the fault detection unit outputs a PWM fault signal to an arithmetic unit and the second buffer unit. In response to the input of the PWM fault signal, the second buffer unit sets the output thereof to high impedance and drives the inverter circuit by a protection operation PWM signal to perform protection operation of a motor.