Three-Phase Inverter PWM Pulse Timing Shift for Capacitor Ripple Reduction
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Solution Overview
Problem
Three-phase inverters face challenges in reducing high-frequency components in bus currents, leading to increased capacitor temperature and device size and cost due to existing space vector control methods, which result in overheating, reduced switching times, and electrical disturbances.
Innovation Solution
A three-phase inverter design with three series circuits connected in parallel to a DC voltage source, where each series circuit includes two semiconductor switching elements, controls PWM pulses to minimize overlapping ranges between positive or negative side pulses, reducing high-frequency components in bus currents and thereby suppressing capacitor temperature rise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If space vector control method is used to reduce high-frequency components in bus currents, then capacitor temperature rise is suppressed, but device size and cost increase due to larger capacitor requirements
Solution Approach 1:
The patent changes the timing parameters of PWM pulses by introducing a shift amount (Δt) that adjusts the relative timing between PWM pulses of different phases. This parameter modification optimizes the bus current waveform to reduce high-frequency components, thereby reducing capacitor temperature rise without requiring larger capacitor size
2Temperature
If space vector control method is used to reduce high-frequency components in bus currents, then capacitor temperature rise is suppressed, but device cost increases due to larger capacitor requirements
Solution Approach 1:
The patent modifies the timing parameters of PWM pulses by introducing a shift amount (Δt) that adjusts the relative timing between PWM pulses of different phases. This parameter optimization reduces high-frequency current components, thereby reducing capacitor temperature rise and allowing the use of smaller, less expensive capacitors
3Loss of time
If PWM pulses are generated with overlapping positive side pulses, then switching times are reduced, but high-frequency components in bus currents increase causing capacitor overheating
Solution Approach 1:
The patent introduces a timing shift parameter (Δt) that optimizes the relative positioning of PWM pulses. By adjusting this parameter, the patent achieves a balance between minimizing switching times and reducing high-frequency current components that cause capacitor overheating
Solution Approach 2:
The patent dynamically adjusts the timing of PWM pulses based on the timing shift amount (Δt). This dynamic timing adjustment allows optimization of both switching efficiency and reduction of high-frequency components, preventing capacitor overheating while maintaining fast switching
Data Source
AI summary
A three-phase inverter includes three series circuits that are connected in parallel to a capacitor connected in parallel to a DC voltage source. Each of the three series circuits includes two semiconductor switching elements connected in series. A connection point between the two semiconductor switching elements is used as an AC output terminal for each phase. The three-phase inverter generates PWM pulses of three phases including a PWM pulse of one phase, whose pulse width of a positive side pulse in one switching cycle is the largest, and including PWM pulses of the other two phases such that a positional relationship between positive side pulses of the other two phases is a positional relationship in which an overlapping range on a time axis is smaller as compared with a state in which a positive side pulse of one phase encompasses a positive side pulse of the other pulse.